ZHCSEC5D November 2015 – May 2021 TPS65235
PRODUCTION DATA
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | TONEAMP | R/W | 0 | 1: 22 kHz tone amplitude is 750 mV (typ) 0: 22 kHz tone amplitude is 650 mV (typ) |
| 6 | TIMER | R/W | 0 | 1: Hiccup ON/OFF time set to 8 ms / 256 ms 0: Hiccup ON/OFF time set to 4 ms / 128 ms |
| 5 | ISW | R/W | 0 | 1: Boost switch peak current limit set to 5 x Iocp + 0.8 A 0: Boost switch peak current limit set to 3 x Iocp + 0.8 A |
| 4 | FSET | R/W | 0 | 1: 500 kHz switching frequency 0: 1 MHz switching frequency |
| 3 | EN | R/W | 1 | 1: LNB output voltage Enabled 0: LNB output disabled |
| 2 | DOUTMODE | R/W | 0 | 1: Reserved, cannot set to "1" 0: DOUT is kept to low when DIN has the tone input |
| 1 | TONE_AUTO | R/W | 0 | 1: GDR (External bypass FET control) is automatically controlled by 22 kHz tones transmit 0: GDR (External bypass FET control) is controlled by TONE_TRANS |
| 0 | TONE_TRANS | R/W | 1 | 1: GDR output with VCP voltage. Bypass FET is ON for tone transmit from TPS65235 0: GDR output with VLNB voltage for tone receive. Bypass FET is OFF for tone receiving from satellite |
| TONE_AUTO | TONE_TRANS | Bypass FET |
|---|---|---|
| 0 | 0 | OFF |
| 0 | 1 | ON |
| 1 | x | Auto Detect |
TPS65235 has full range of diagnostic flags for operation and debug. Processor can read the status register to check the error conditions. Once the error happens, the flags are changed, once the errors are gone, the flags are set back without I2C access.
If flags TSD and OCP are triggered, FAULT pin will be pulled low, so FAULT pin can be the interrupt signal to processor. Once TSD and OCP are set to “1”, the FAULT pin logic is latched to low, processor need to read this status register in order to release the fault conditions.