ZHCSEC5D November 2015 – May 2021 TPS65235
PRODUCTION DATA
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| OUTPUT VOLTAGE | ||||||
| tr, tf | 13 V to 18 V transition rising falling time | C(TCAP) = 22 nF | 2 | ms | ||
| tON(min) | Minimum on time for the Low side FET | 75 | 102 | 130 | ns | |
| TONE | ||||||
| tr(tone) | Tone rise time | IO = 0 mA to 500 mA, CO = 100 nF, Control Reg1[0] = 0 | 11 | µs | ||
| IO = 0 mA to 500 mA, CO = 100 nF, Control Reg1[0] = 1, and EXTM has 44 kHz input | 5.5 | µs | ||||
| tf(tone) | Tone fall time | IO = 0 mA to 500 mA, CO = 100 nF, Control Reg1[0] = 0 | 10.8 | µs | ||
| IO = 0 mA to 500 mA, CO = 100 nF, Control Reg1[0] = 1, and EXTM has 44 kHz input | 5.4 | µs | ||||
| PROTECTION | ||||||
| tON | Overcurrent protection ON Time | TIMER=0 | 2.3 | 3.75 | 5.52 | ms |
| tOFF | Overcurrent protection OFF Time | TIMER=0 | 98.5 | 118 | 133.5 | ms |
| I2C INTERFACE | ||||||
| tBUF | Bus free time between a STOP and START condition | 1.3 | µs | |||
| tHD_STA | Hold time (repeated) START condition | 0.6 | µs | |||
| tSU_STO | Setup time for STOP condition | 0.6 | µs | |||
| tLOW | LOW period of the SCL clock | 1.3 | µs | |||
| tHIGH | HIGH period of the SCL clock | 0.6 | µs | |||
| tSU_STA | Setup time for a repeated START condition | 0.6 | µs | |||
| tSU_DAT | Data setup time | 0.1 | µs | |||
| tHD_DAT | Data hold time | 0 | 0.9 | µs | ||
| tRCL | Rise time of SCL signal | Capacitance of one bus line (pF) | 20 + 0.1 CB | 300 | ns | |
| tRCL1 | Rise time of SCL Signal after a Repeated START condition and after an acknowledge BIT | Capacitance of one bus line (pF) | 20 + 0.1 CB | 300 | ns | |
| tFCL | Fall time of SCL signal | Capacitance of one bus line (pF) | 20 + 0.1 CB | 300 | ns | |
| tRDA | Rise time of SDA signal | Capacitance of one bus line (pF) | 20 + 0.1 CB | 300 | ns | |
| tFDA | Fall time of SDA signal | Capacitance of one bus line (pF) | 20 + 0.1 CB | 300 | ns | |
| CB | Capacitance of one bus line(SCL and SDA) | 400 | pF | |||