ZHCSEC5D November 2015 – May 2021 TPS65235
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Boost Converter
- 7.3.2 Linear Regulator and Current Limit
- 7.3.3 Boost Converter Current Limit
- 7.3.4 Charge Pump
- 7.3.5 Slew Rate Control
- 7.3.6 Short Circuit Protection, Hiccup and Overtemperature Protection
- 7.3.7 Tone Generation
- 7.3.8 Tone Detection
- 7.3.9 Disable and Enable
- 7.3.10 Component Selection
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6 Register Maps
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
7.5.2 TPS65235 I2C Update Sequence
The TPS65235 requires a start condition, a valid I2C address, a register address byte, and a data byte for a single update. After the receipt of each byte, TPS65235 device acknowledges by pulling the SDA line low during the high period of a single clock pulse. TPS65235 performs an update on the falling edge of the LSB byte.
When the TPS65235 is disabled (EN pin tied to ground) the device cannot be updated via the I2C interface.
Figure 7-10 I2C Write Data Format
Figure 7-11 I2C Read Data Format