The TPS65262-1 supports a 2-layer PCB layout, shown in Figure 9-34.

Layout is a critical portion of good power supply design. See Figure 9-34 for a PCB layout example. The top contains the main power traces for VIN, VOUT, and LX. The top layer also has connections for the remaining pins of the TPS65262-1 and a large top-side area filled with ground. The top-layer ground area must be connected to the bottom-layer ground using vias at the input bypass capacitor, the output filter capacitor, and directly under the TPS65262-1 device to provide a thermal path from the exposed thermal pad land to ground. The bottom layer acts as a ground plane connecting analog ground and power ground.

For operation at full-rated load, the top-side ground area and bottom-side ground plane must provide adequate heat dissipating area. Several signals paths conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supply's performance. To help eliminate these problems, the VIN pin must be bypassed to ground with a low-ESR ceramic bypass capacitor with X5R or X7R dielectric. Take care to minimize the loop area formed by the bypass capacitor connections, VIN pins, and ground connections. The VIN pin must also be bypassed to ground using a low-ESR ceramic capacitor with X5R or X7R dielectric.

Because the LX connection is the switching node, the output inductor must be located close to the LX pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The output filter capacitor ground must use the same power ground trace as the VIN input bypass capacitor. Try to minimize this conductor length while maintaining adequate width. The small signal components must be grounded to the analog ground path.

The FB and COMP pins are sensitive to noise so the resistors and capacitors must be located as close as possible to the IC and routed with minimal lengths of trace. The additional external components can be placed approximately as shown in Figure 9-34.