The TPS65262-1 has a dedicated enable pin for each converter. The converter enable pins are biased by a current source that allows for easy sequencing with the addition of an external capacitor. Disabling the converter with an active pulldown transistor on the ENx pin allows for a predictable power-down timing operation. Figure 8-3 shows the timing diagram of a typical buck power-up sequence with a capacitor connected at ENx pin.

A typical 1.4-µA current charges the ENx pin from the input supply when the ENx pin voltage is lower than typical 0.4 V. The internal V7V LDO turns on when the ENx pin voltage rises to typical 0.4 V and a 3.6-µA pullup current sources ENx. After the ENx pin voltage reaches 1.2 V typical, 3-µA hysteresis current sources to the pin to improve noise sensitivity. If all output voltages are in regulation, PGOOD is asserted after PGOOD deglitch time.

Figure 8-3 Startup Power Sequence