The TPS65263-1Q1 incorporates a peak current mode control scheme. The error amplifier is a transconductance amplifier with a gain of 300 µS. A typical type II compensation circuit adequately delivers a phase margin between 40° and 90°. C_b adds a high-frequency pole to attenuate high-frequency noise when needed. To calculate the external compensation components, follow these steps.

1. Select switching frequency, ƒ_sw, that is appropriate for application depending on L and C sizes, output ripple, EMI, and so forth. Switching frequency between 500 kHz to 1 MHz gives best trade-off between performance and cost. To optimize efficiency, lower switching frequency is desired.
2. Set up crossover frequency, ƒ_c, which is typically between 1/5 and 1/20 of ƒ_sw.
3. R_C can be determined by:
   Equation 18.

   where

   • G_{m_EA} is the error amplifier gain (300 µS).
   • G_{m_PS} is the power stage voltage to current conversion gain (7.4 A/V).
4. Calculate C_C by placing a compensation zero at or before the dominant pole .
   Equation 19.
5. Optional C_b can be used to cancel the zero from the ESR associated with C_O.
   Equation 20.
6. Type III compensation can be implemented with the addition of one capacitor, C₁. This allows for slightly higher loop bandwidths and higher phase margins. If used, calculate C₁ from Equation 21.
   Equation 21.

Figure 8-2 DC/DC Loop Compensation