The TPS65263-1Q1 has a dedicated enable pin and soft-start pin for each converter. The converter enable pins are biased by a current source that allows for easy sequencing by the addition of an external capacitor. Disabling the converter with an active pulldown transistor on the ENx pin allows for predictable power-down timing operation. Figure 7-8 shows the timing diagram of a typical buck power-up sequence with connecting a capacitor at the ENx pin.

A typical 1.4-µA current is charging the ENx pin from input supply. When the ENx pin voltage rises to typical 0.4 V, the internal V7V LDO turns on. A 3.9-µA pullup current is sourcing ENx. After the ENx pin voltage reaches the ENx enabling threshold, a 3.0-µA hysteresis current sources to the pin to improve noise sensitivity. The internal soft-start comparator compares the SS pin voltage to 1.2 V. When the SS pin voltage ramps up to 1.2 V, PGOOD monitor is enabled. After PGOOD deglitch time, PGOOD is deasserted. The SS pin voltage is eventually clamped around 2.1 V.

Figure 7-8 Start-up Power Sequence