The TPS65263 has dedicated enable pin and soft-start pin for each converter. The converter enable pins are biased by a current source that allows for easy sequencing by the addition of an external capacitor. Disabling the converter with an active pull-down transistor on the ENs pin allows for a predictable power-down timing operation. Figure 8-8 shows the timing diagram of a typical buck power-up sequence with connecting a capacitor at ENx pin.

A typical 1.4-µA current is charging ENx pin from input supply. When ENx pin voltage rise to typical 0.4 V, the internal V7V LDO turns on. A 3.8-µA pullup current is sourcing ENx. After ENx pin voltage reaches to ENx enabling threshold, 3-µA hysteresis current sources to the pin to improve noise sensitivity. The internal soft-start comparator compares SS pin voltage to 1.2 V. When SS pin voltage ramps up to 1.2 V, PGOOD monitor is enabled. After PGOOD deglitch time, PGOOD is deasserted. SS pin voltage eventually is clamped around
2.1 V.

Figure 8-8 Startup Power Sequence