The TPS65263 is a monolithic triple synchronous step-down (buck) converter with 3-A/2-A/2-A output currents. A wide 4.5- to 18-V input supply voltage range encompasses most intermediate bus voltages operating off 5-, 9-, 12-, or 15-V power bus. The feedback voltage reference for each buck is 0.6 V. Each buck is independent with dedicated enable, soft-start and loop compensation pins.

The TPS65263 is equipped with I²C compatible bus for communication with SoC to control buck converters. Through I²C interface, SoC can enable or disable the buck converters, set output voltage and read status registers. External feedback divider resistors can set the initial start-up voltage of the buck regulators. After the voltage identification VID DAC is updated via the I²C, output voltage of the buck regulators can be independently programmed with 7 bits VID from 0.68 to 1.95 V in 10-mV voltage step resolution. Output voltage of the buck regulators transition begins after the I²C interface receives the command for GO bit in command register.

In light loading condition, the converter will automatically operate in pulse skipping mode (PSM) to save power. The PSM can be disabled through I²C so that the converter operates at continuous current mode (CCM) at light load with a fixed frequency for optimized output ripple.

The TPS65263 implements a constant frequency, peak current mode control that simplifies external loop compensation. The device operates in fixed 600 kHz. The switch clock of buck1 is 180° out-of-phase operation from the clock of buck2 and buck3 channels to reduce input current ripple, input capacitor size and power supply induced noise.

The TPS65263 is designed for safe monotonic startup into pre-biased loads. The default start up is when VIN is typically 4.25 V. The ENx pin also can be used to adjust the input voltage UVLO with an external resistor divider. In addition, the ENx pin has an internal 3.8-µA current source, so the EN pin can be floating for automatically powering up the converters.

The TPS65263 reduces the external component count by integrating the bootstrap circuit. The bias voltage for the integrated high-side MOSFET is supplied by a capacitor between the BST and LX pins. A UVLO circuit monitors the bootstrap capacitor voltage VBST-VLX in each buck. When VBST-VLX voltage drops to the threshold, LX pin is pulled low to recharge the bootstrap capacitor. The TPS65263 can operate at 100% duty cycle as long as the bootstrap capacitor voltage is higher than the BOOT-LX UVLO threshold which is typically 2.1 V.

The TPS65263 has power good comparators with hysteresis, which monitor the output voltages through internal feedback voltages. I²C can read the power good status with commanding register.

The SS (soft start/tracking) pin is used to minimize inrush currents or provide power supply sequencing during power up. A small value capacitor or resistor divider is connected the pin for soft start or voltage tracking.

The TPS65263 is protected from overload and over temperature fault conditions. The converter minimizes excessive output overvoltage transients by taking advantage of the power good comparator. When the output is over, the high-side MOSFET is turned off until the internal feedback voltage is lower than 105% of the 0.6-V reference voltage. The TPS65263 implements both high-side MOSFET overload protection and bidirectional low-side MOSFET overload protections to avoid inductor current runaway. If the overcurrent condition has lasted for more than the OC wait time (0.5ms typical), the converter will shut down and re-start after the hiccup time (14ms typical). The TPS65263 shuts down if the junction temperature is higher than thermal shutdown trip point. When the junction temperature drops 20°C typically below the thermal shutdown trip point, the TPS65263 will be restarted under control of the soft start circuit automatically.