The TPS65268-Q1 device incorporates a peak current-mode control scheme. The error amplifier is a transconductance amplifier with a gain of 300 µS. A typical type II compensation circuit adequately delivers a phase margin from 40° to 90°. The C_b capacitor adds a high-frequency pole to attenuate high-frequency noise when needed. To calculate the external compensation components, follow these steps:

1. Select a switching frequency, f_SW, that is appropriate for the application depending on the inductor size, capacitor size, output ripple, EMI, and so forth. Selecting the switching frequency is a trade-off between performance and cost. To achieve a smaller size and lower cost, a higher switching frequency is desired. To optimize efficiency, a lower switching frequency is desired.
2. Set up the crossover frequency, f_C, which is typically from 1/5 to 1/20 of f_SW.
3. Use Equation 16 to calculate the value of R_C.
   Equation 16.

   where

   • G_{m_EA} is the error amplifier gain (300 µS).
   • G_{m_PS} is the power stage voltage to current conversion gain (7.4 A/V).
4. Use Equation 17 to calculate the value C_c by placing a compensation zero at or before the dominant pole ( ).
   Equation 17.
5. Optional: Use Equation 18 to calculate the value of C_B capacitor to cancel the zero from the ESR associated with C_O.
   Equation 18.
6. Optional: Implement type III compensation with the addition of one capacitor, C1. This implementation allows for slightly higher loop bandwidths and higher phase margins. If used, used Equation 19 to calculate the value of C1.
   Equation 19.

Figure 8-2 DC-DC Loop Compensation