The TPS65268-Q1 device has a dedicated enable pin and soft-start pin for each converter. The converter enable pins are biased by a current source that allows for easy sequencing by the addition of an external capacitor. Disabling the converter with an active pulldown transistor on the ENx pin allows for predictable power-down timing operation. Figure 7-7 shows the timing diagram of a typical buck power-up sequence with connecting a capacitor at the ENx pin.

A typical 1.4-µA current is charging the ENx pin from the input supply. When the ENx pin voltage rises to typical 0.4 V, the internal V7V LDO regulator turns on. A 3.9-µA pullup current sources the ENx pin. After the ENx pin voltage reaches the ENx enabling threshold, a 3-µA hysteresis current sources to the pin to improve noise sensitivity. The internal soft-start comparator compares the SSx pin voltage to 1.2 V. When the SSx pin voltage ramps up to 1.2 V, PGOOD monitor is enabled. After PGOOD deglitch time, PGOOD is deasserted. The SSx pin voltage is eventually clamped around 2.1 V.

Figure 7-7 Startup Power Sequence