In any of the operating states (RESET, DIAGNOSTIC, ACTIVE, and SAFE), if the BUCK2 switching-clock error is detected, while the internal OSC clock source is in good condition, the following occurs:

• The BUCK2_FSW_CLK_ERR status bit is set.
• The BUCK2 regulator is disabled without activating resistive discharge.
• The device goes into the SAFE state.
• The device error counter increments.
• The ENDRV/nIRQ pin is asserted low to interrupt the external system MCU.

If the BUCK2 regulator is configured as an NRES source and when the BUCK2 output discharges to less than its UV-threshold level, the device goes into the RESET state. In the RESET state, the BUCK2 regulator is enabled again only after the BUCK2 regulator has discharged below the V_{BUCK2_RESTART_LEVEL} voltage level and the f_{SW_BUCK2} clock monitor indicates that the clock is in good condition. Enabling the BUCK2 regulator again is followed by a full ABIST run during the NRES extension after there is no active RESET state condition.

If an ABIST run in the RESET state fails, the device goes into the SAFE state again, repeating the same procedure until the device error counter reaches its power-down threshold (the PWD_TH[3:0] bits). When the device error counter reaches its programmed power-down threshold, the device goes into the OFF state.

While the device is in the SAFE state, the system MCU can detect if a reported clock failure occurred because of a clock-monitor failure or true clock failure. A false clock failure occurs when a clock monitor fails. In case of false clock-failure detection, the system MCU can disable the clock monitoring. As a single-point failure, the clock monitoring failure is not a critical failure, and therefore, the system MCU can ignore it.

While the device is in the RESET state and when the BUCK2 regulator is enabled again, the device goes into the OFF state, if the BUCK2 regulator does not ramp-up within the time-out interval for the RESET state.

If the BUCK2 regulator is not configured as a RESET state condition (BUCK2_UV_RST_EN = 0b), the device does not change the state as the BUCK2 output discharges to less than its UV threshold level. The system MCU can enable the BUCK2 regulator by setting the BUCK2_EN control bit in the PWR_CTRL control register.