ZHCSL05C October   2019  – October 2023 TPS65313-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 器件功能方框图
  6. 5 Revision History
  7. 6 说明（续）
  8. 7 Device Option Table
  9. 8 Pin Configuration and Functions
  10. 9 Specifications
    1. 9.1  Absolute Maximum Ratings
    2. 9.2  ESD Ratings
    3. 9.3  Recommended Operating Conditions
    4. 9.4  Thermal Information
    5. 9.5  Power-On-Reset, Current Consumption, and State Timeout Characteristics
    6. 9.6  PLL/Oscillator and SYNC_IN Pin Characteristics
    7. 9.7  Wide-VIN Synchronous Buck Regulator (Wide-VIN BUCK) Characteristics
    8. 9.8  Low-Voltage Synchronous Buck Regulator (LV BUCK) Characteristics
    9. 9.9  Synchronous Boost Converter (BOOST) Characteristics
    10. 9.10 Internal Voltage Regulator (VREG) Characteristics
    11. 9.11 Voltage Monitors for Regulators Characteristics
    12. 9.12 External General Purpose Voltage Monitor Characteristics
    13. 9.13 VIN and VIN_SAFE Under-Voltage and Over-Voltage Warning Characteristics
    14. 9.14 WAKE Input Characteristics
    15. 9.15 NRES (nRESET) Output Characteristics
    16. 9.16 ENDRV/nIRQ Output Characteristics
    17. 9.17 Analog DIAG_OUT
    18. 9.18 Digital INPUT/OUTPUT IOs (SPI Interface IOs, DIAG_OUT/SYNC_OUT, MCU_ERROR)
    19. 9.19 BUCK1, BUCK2, BOOST Thermal Shutdown / Over Temperature Protection Characteristics
    20. 9.20 PGNDx Loss Detection Characteristics
    21. 9.21 SPI Timing Requirements
    22. 9.22 SPI Characteristics
    23. 9.23 Typical Characteristics
  11. 10Parameter Measurement Information
  12. 11Detailed Description
    1. 11.1  Overview
    2. 11.2  Functional Block Diagram
    3. 11.3  Wide-VIN Buck Regulator (BUCK1)
      1. 11.3.1 Fixed-Frequency Voltage-Mode Step-Down Regulator
      2. 11.3.2 Operation
      3. 11.3.3 Voltage Monitoring (Monitoring and Protection)
      4. 11.3.4 Overcurrent Protection (Monitoring and Protection)
      5. 11.3.5 Thermal Warning and Shutdown Protection (Monitoring and Protection)
      6. 11.3.6 Overvoltage Protection (OVP) (Monitoring and Protection)
      7. 11.3.7 Extreme Overvoltage Protection (EOVP) (Monitoring and Protection)
    4. 11.4  Low-Voltage Buck Regulator (BUCK2)
      1. 11.4.1 Fixed-Frequency Peak-Current Mode Step-Down Regulator
      2. 11.4.2 Operation
      3. 11.4.3 Output Voltage Monitoring (Monitoring and Protection)
      4. 11.4.4 Overcurrent Protection (Monitoring and Protection)
      5. 11.4.5 Thermal Sensor Warning and Thermal Shutdown Protection (Monitoring and Protection)
      6. 11.4.6 Overvoltage Protection (OVP) (Monitoring and Protection)
    5. 11.5  Low-Voltage Boost Converter (BOOST)
      1. 11.5.1 Output Voltage Monitoring (Monitoring and Protection)
      2. 11.5.2 Overcurrent Protection (Monitoring and Protection)
      3. 11.5.3 Thermal Sensor Warning and Shutdown Protection (Monitoring and Protection)
      4. 11.5.4 Overvoltage Protection (OVP) (Monitoring and Protection)
    6. 11.6  VREG Regulator
    7. 11.7  BUCK1, BUCK2, and BOOST Switching Clocks and Synchronization (SYNC_IN) Clock
      1. 11.7.1 Internal fSW Clock Configuration (fSW Derived from an Internal Oscillator)
      2. 11.7.2 BUCK1 Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      3. 11.7.3 BUCK2 Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      4. 11.7.4 BOOST Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      5. 11.7.5 External fSW Clock Configuration (fSW Derived from SYNC_IN and PLL Clocks)
        1. 11.7.5.1 SYNC_IN, PLL, and VCO Clock Monitors
        2. 11.7.5.2 BUCK1 Switching Clock-Monitor Error (External fSW Clock Configuration)
        3. 11.7.5.3 BUCK2 Switching Clock-Monitor Error (External fSW Clock Configuration)
        4. 11.7.5.4 BOOST Switching Clock-Monitor Error (External fSW Clock Configuration)
    8. 11.8  BUCK1, BUCK2, and BOOST Switching-Clock Spread-Spectrum Modulation
    9. 11.9  Monitoring, Protection and Diagnostics Overview
      1. 11.9.1  Safety Functions and Diagnostic Overview
      2. 11.9.2  Supply Voltage Monitor (VMON)
      3. 11.9.3  Clock Monitors
      4. 11.9.4  Analog Built-In Self-Test
        1. 11.9.4.1 ABIST During Power-Up or Start-Up Event
        2. 11.9.4.2 ABIST in the RESET state
        3. 11.9.4.3 ABIST in the DIAGNOSTIC, ACTIVE, and SAFE State
        4. 11.9.4.4 ABIST Scheduler in the ACTIVE State
      5. 11.9.5  Logic Built-In Self-Test
      6. 11.9.6  Junction Temperature Monitors
      7. 11.9.7  Current Limit
      8. 11.9.8  Loss of Ground (GND)
      9. 11.9.9  Diagnostic Output Pin (DIAG_OUT)
        1. 11.9.9.1 Analog MUX Mode on DIAG_OUT
        2. 11.9.9.2 Digital MUX Mode on DIAG_OUT
          1. 11.9.9.2.1 MUX-Output Control Mode
          2. 11.9.9.2.2 Device Interconnect Mode
      10. 11.9.10 Watchdog
        1. 11.9.10.1 WD Question and Answer Configurations
        2. 11.9.10.2 WD Failure Counter and WD Status
        3. 11.9.10.3 WD SPI Event Definitions
        4. 11.9.10.4 WD Q&A Sequence Run
        5. 11.9.10.5 WD Question and Answer Value Generation
          1. 11.9.10.5.1 WD Initialization Events
      11. 11.9.11 MCU Error Signal Monitor
      12. 11.9.12 NRES Driver
      13. 11.9.13 ENDRV/nIRQ Driver
      14. 11.9.14 CRC Protection for the Device Configuration Registers
      15. 11.9.15 CRC Protection for the Device EEPROM Registers
    10. 11.10 General-Purpose External Supply Voltage Monitors
    11. 11.11 Analog Wake-up and Failure Latch
    12. 11.12 Power-Up and Power-Down Sequences
    13. 11.13 Device Fail-Safe State Controller (Monitoring and Protection)
      1. 11.13.1 OFF State
      2. 11.13.2 INIT State
      3. 11.13.3 RESET State (ON Transition From the INIT State)
      4. 11.13.4 RESET State (ON Transition From DIAGNOSTIC, ACTIVE, and SAFE State)
      5. 11.13.5 DIAGNOSTIC State
      6. 11.13.6 ACTIVE State
      7. 11.13.7 SAFE State
      8. 11.13.8 State Transition Priorities
    14. 11.14 Wakeup
    15. 11.15 Serial Peripheral Interface (SPI)
      1. 11.15.1 SPI Command Transfer Phase
      2. 11.15.2 SPI Data Transfer Phase
      3. 11.15.3 Device SPI Status Flag Response Byte
      4. 11.15.4 Device SPI Data Response
      5. 11.15.5 Device SPI Master CRC (MCRC) Input
      6. 11.15.6 Device SPI Slave CRC (SCRC) Output
      7. 11.15.7 SPI Frame Overview
    16. 11.16 Register Maps
      1. 11.16.1 Device SPI Mapped Registers
        1. 11.16.1.1 Memory Maps
          1. 11.16.1.1.1 SPI Registers
  13. 12Applications, Implementation, and Layout
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
      2. 12.2.2 Detailed Design Procedure
        1. 12.2.2.1  Selecting the BUCK1, BUCK2, and BOOST Output Voltages
        2. 12.2.2.2  Selecting the BUCK1, BUCK2, and BOOST Inductors
        3. 12.2.2.3  Selecting the BUCK1 and BUCK2 Output Capacitors
        4. 12.2.2.4  Selecting the BOOST Output Capacitors
        5. 12.2.2.5  Input Filter Capacitor Selection for BUCK1, BUCK2, and BOOST
        6. 12.2.2.6  Input Filter Capacitors on AVIN and VIN_SAFE Pins
        7. 12.2.2.7  Bootstrap Capacitor Selection
        8. 12.2.2.8  Internal Linear Regulator (VREG) Output Capacitor Selection
        9. 12.2.2.9  EXTSUP Pin
        10. 12.2.2.10 WAKE Input Pin
        11. 12.2.2.11 VIO Supply Pin
        12. 12.2.2.12 External General-Purpose Voltage Monitor Input Pins (EXT_VSENSE1 and EXT_VSENSE2)
        13. 12.2.2.13 SYNC_IN Pin
        14. 12.2.2.14 MCU_ERR Pin
        15. 12.2.2.15 NRES Pin
        16. 12.2.2.16 ENDRV/nIRQ Pin
        17. 12.2.2.17 DIAG_OUT Pin
        18. 12.2.2.18 SPI Pins (NCS,SCK, SDI, SDO)
        19. 12.2.2.19 PBKGx, AGND, DGND, and PGNDx Pins
        20. 12.2.2.20 Calculations for Power Dissipation and Junction Temperature
          1. 12.2.2.20.1 BUCK1 Output Current Calculation
          2. 12.2.2.20.2 Device Power Dissipation Estimation
          3. 12.2.2.20.3 Device Junction Temperature Estimation
            1. 12.2.2.20.3.1 Example for Device Junction Temperature Estimation
      3. 12.2.3 Application Curves
      4. 12.2.4 Layout
        1. 12.2.4.1 Layout Guidelines
        2. 12.2.4.2 Layout Example
        3. 12.2.4.3 Considerations for Board-Level Reliability (BLR)
    3. 12.3 Power Supply Coupling and Bulk Capacitors
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 接收文档更新通知
    3. 13.3 支持资源
    4. 13.4 Trademarks
    5. 13.5 静电放电警告
    6. 13.6 术语表
  15. 14Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9.7 Wide-VIN Synchronous Buck Regulator (Wide-VIN BUCK) Characteristics

TA = -40°C to 125°C, TJ up to 150°C, unless otherwise noted.(1)
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
3.0 fSW_BUCK1 Wide-VIN BUCK switching frequency 6V ≤ VIN/AVIN/VIN_SAFE ≤ 36V 2.0 2.2 2.4 MHz
3.1a VIN Wide-VIN BUCK supply voltage VBUCK1 = 3.3 V 4.0 36 V
3.1b VIN Wide-VIN BUCK supply voltage VBUCK1 = 3.6 V 4.3 36 V
3.2a VBUCK1 Wide-VIN BUCK output voltage 3.3 V
3.2b VBUCK1 Wide-VIN BUCK output voltage 3.6 V
3.3 VBUCK1_DC_ACCURACY Wide-VIN BUCK DC output voltage accuracy 6 V ≤ VIN/AVIN/VIN_SAFE ≤ 18 V, measured at VSENSE1 pin(3) –1.7 1.7 %
3.4a IBUCK1_LOAD Wide-VIN BUCK load current(2) min(VIN) ≤ VIN/AVIN/VIN_SAFE ≤ 6V (4) Refer to
Figure 9.5		 A
6 V ≤ VIN/AVIN/VIN_SAFE ≤ 18 V 3.1 A
3.5a VBUCK1_RIPPLE Wide-VIN BUCK output peak voltage ripple (0.5 × VPP), in percentage of target regulation voltage 6 V ≤ VIN/AVIN/VIN_SAFE ≤ 18 V, IBUCK1_LOAD = 0 A to max(IBUCK1_LOAD) (3)
 0.3 %
3.5b VBUCK1_RIPPLE_SSM Wide-VIN BUCK output peak voltage ripple (0.5 × VPP), in percentage of target regulation voltage, when fSW clock spread spectrum modulation is enabled 6 V ≤ VIN/AVIN/VIN_SAFE ≤ 18 V, IBUCK1_LOAD = 0 A to max(IBUCK1_LOAD) (3)
 0.3 %
3.6 RDSON_HS_BUCK1 ON resistance of high-side switch FET VGS=4.5V, IDS = 0.7A 150 250 mΩ
3.7 RDSON_LS_BUCK1 ON resistance of low-side switch FET VGS=4.5V, IDS = 0.7A 80 150 mΩ
3.10 tSS_BUCK1 Wide-VIN BUCK internal soft-start duration Measured from Wide-VIN BUCK enable event to VBUCK1 crossing its UV threshold.
CBUCK1 = 100 µF		 1 ms
3.12a IHS_SCG_ILIM_BUCK1 High side switch current limit for weak-short/hard-short conditions 4 5.5 7 A
3.12b IHS_OVC_ILIM_BUCK1 High side switch current limit for over-load conditions. 3.8 5 A
3.12c IHS_SCG_ILIM_BUCK1/IHS_OVC_ILIM_BUCK1 Ratio between short-circuit current limit and over-load current limit for high-side switch 1.43 A/A
3.13a ILS_SCG_ILIM_BUCK1 Low side switch current limit for weak-short/hard-short conditions
 4 5.5 7 A
3.13b ILS_OVC_ILIM_BUCK1 Low side switch current limit for over-load conditions 3.8 5 A
3.13c ILS_SCG_ILIM_BUCK1/ILS_OVC_ILIM_BUCK1 Ratio between short-circuit current limit and over-load current limit for low-side switch 1.43 A/A
3.14 ILS_SINK_BUCK1 Low side sinking current limit -2.5 -2 -1.40 A
3.18a RDISCH_BUCK1 Wide-VIN BUCK internal discharge resistance when device is in RESET state Wide-VIN BUCK disabled, VBUCK1 = 1 V 100 180 400 Ω
3.18b RDISCH_BUCK1_OFF Wide-VIN BUCK internal discharge resistance when device is in OFF state Wide-VIN BUCK disabled, VBUCK1 = 1 V 400 800 1200 Ω
3.19 ∆VBUCK1_LINEREG_DC Output voltage line regulation

NOTE: DC line regulation as output voltage change in % (∆VBUCK1 / VBUCK1 ) as VIN is changing from 6 V to 18 V		 6 V ≤ VIN/AVIN/VIN_SAFE ≤ 18 V, IBUCK1_LOAD = 1.5 A (3) 0.1 0.2 %
3.20 ∆VBUCK1_LOADREG_DCWide-VIN  Output voltage load regulation NOTE: DC load regulation as output voltage change in % (∆VBUCK1 / VBUCK1 ) as IBUCK1_LOAD changes from 0A to max(IBUCK1_LOAD) 6 V ≤ VIN/AVIN/VIN_SAFE ≤ 18 V (3) 0.1 0.2 %
3.21a VBUCK1_BUCK1_LOAD_TRAN1 Load transient regulation, in percentage of steady-state regulation voltage 6 V ≤ VIN/AVIN/VIN_SAFE ≤ 18 V, IBUCK1_LOAD load steps:
- 0.5 A to 1.5 A
- 1.5 A down to 0.5 A
dIBUCK1_LOAD/dt = 300 mA/μs (3)		 -3 3 %
3.21b VBUCK1_LOAD_TRAN2 Load transient regulation, in percentage of steady-state regulation voltage 6 V ≤ VIN/AVIN/VIN_SAFE ≤ 18 V, IBUCK1_LOAD load steps:
- 2 A to 3.1 A
dIBUCK1_LOAD/dt = 60 mA/μs (3)		 -3 3 %
3.21c VBUCK1_LOAD_TRAN3 Load transient regulation, in percentage of steady-state regulation voltage 6 V ≤ VIN/AVIN/VIN_SAFE ≤ 18 V, IBUCK1_LOAD load steps:
- 3.1 A to 1 A
dIBUCK1_LOAD/dt = 100 mA/μs (3)		 -3 3 %
3.22 tSETTLE_BUCK1 Load transient recovery time to 1% below starting point or 1% above starting point.  Refer to 3.21a, 3.21b, and 3.21c. 20 µs
3.24a ηBUCK1 Wide-VIN BUCK Efficiency VIN/AVIN/VIN_SAFE = 13 V, VBUCK1=3.3V, IBUCK1_LOAD = 1.5 A
Other conditions covered in efficiency plot diagram		 83 %
3.26 VBUCK1_RESTART_LEVEL Wide-VIN BUCK output voltage level before ramp-up starts, in percentage of target regulation voltage After wide-VIN BUCK regulator is shutdown its output voltage is discharged below this level before a new start-up event. 45 %
(1) Total output capacitance, CBUCK1, including board parasitic capacitance, should not exceed 100 μF.
(2) Advanced thermal design may be required to avoid thermal shutdown.
(3) Refer to Regulator LC Selection table for inductor and capacitor values.
(4) Some of the BUCK1 performance electrical parameters may not be met when VIN/AVIN/VIN_SAFE ≤ 6.
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