Currents through both the high-side (HS) power MOSFET and the low-side (LS) power MOSFET are continuously monitored to protect the internal power MOSFETs from damage. Current through each MOSFET is compared against two threshold levels (I_{HS/LS_SCG_ILIM_BUCK1} and I_{HS/LS_OVC_LIM_BUCK1}). The former is to detect a short-circuit event and the latter is to detect an overload condition where the BUCK1 regulator is loaded with a current higher than what is specified.

If either the HS MOSFET current or the LS MOSFET current exceeds their respective overload current limits (I_{HS_OVC_ILIM_BUCK1} and I_{LS_OVC_ILIM_BUCK1}) an overload event is detected and the BUCK1_OVC status bit is set in the SAFETY_BUCK1_STAT1 register; however, the regulator does not shut down. As the external inductor current continues to increase, and if either the HS MOSFET current or the LS MOSFET current exceeds their respective short-circuit current limit (I_{HS_SCG_ILIM_BUCK1} and I_{LS_SCG_ILIM_BUCK1}), then the HS MOSFET is turned off immediately and the LS MOSFET is turned on, until the inductor current decreases to less than the overload threshold (I_{LS_OVC_ILIM_BUCK1}). The BUCK1 regulator is then disabled and the BUCK1_SCG status bit is set in the SAFETY_BUCK1_STAT1 register. This double-sampling scheme allows for any overcurrent event to be detected either through a HS or LS MOSFET, especially when the BUCK1 regulator operates at a low duty cycle with a high input supply voltage. The BUCK1_SCG_OFF_EN configuration bit setting selects the device response after a short-circuit detection.

If the BUCK1_SCG_OFF_EN bit is set to 1b, the following occurs:

• The BUCK1 regulator, BUCK2 regulator, and BOOST converter are disabled, while enabling discharge through the internal resistor.
• The device goes into the OFF state.
• The BUCK1_SCG status bit is latched in the Analog_Latch (to preserve it) while the device is in the OFF state and presented to the system MCU during the next power-up event from the OFF state.

If the BUCK1_SCG_OFF_EN bit is set to 0b, the following occurs:

• The BUCK1 regulator, BUCK2 regulator, and BOOST converter are disabled, while disabling discharge through the internal resistor.
• The device goes into the SAFE state.
  • Eventually, as the BUCK1 regulator, BUCK2 regulator, and BOOST converter discharges to less than the UV threshold, a global RESET state condition is met, as long as one regulator UV event is configured as a RESET state event (as an example, the BUCK1_UV_RST_EN bit is set to 1b) and the device goes into the RESET state. When the device goes into the RESET state, the BUCK1 regulator is enabled again (its default value). After the BUCK1 output exceeds the UV threshold, the BUCK2 regulator is enabled, followed by the BOOST converter.
  • All the BUCK1 monitoring and protection mechanisms are active, and if any critical condition is still present, the BUCK1 regulator stays disabled. If the BUCK1 regulator never recovers while in the RESET state, the RESET state time-out event puts the device in the OFF state.
• The ENDRV/nIRQ pin is driven low.
• The device error counter increments.

The LS MOSFET is also protected by detection circuitry for cycle-by-cycle sink-current limit. This detection circuitry protects the LS MOSFET from excessive reverse current caused by switching the PH1 or PH1A pin to PGND1 or PGND1A. If the LS sinking current exceeds the I_{LS_SINK_BUCK1} sink-current limit, an event is detected and the BUCK1_LS_SINK_OVC SPI status bit is set in the SAFETY_BUCK1_STAT1 register. If the event duration is longer than 20 µs (typical) the BUCK1 regulator is turned off. The inductor current continues to flow to the supply at the VIN pin through the body diode of the HS MOSFET. The BUCK1_LS_SINK_OVC_OFF_EN configuration bit setting selects the device response after the LS sink current-limit detection.

If the BUCK1_LS_SINK_OVC_OFF_EN bit is set to 1b, the following occurs:

• The device goes into the OFF state.
• The LS sink current limit of the BUCK1 regulator is latched in the Analog_Latch (to preserve it) while the device is in the OFF state and presented to the system MCU during the next power-up event from the OFF state.

If the BUCK1_LS_SINK_OVC_OFF_EN bit is set to 0b, the following occurs:

• The device goes into the SAFE state with all switched-mode regulators disabled and with the resistive discharge circuit disabled.
• The ENDRV/nIRQ pin is driven low to interrupt the system MCU.
• The device error counter increments.

The LS sink current-limit event can also be detected when the regulator is enabled and when its output has not been discharged to less than the voltage level defined by the V_{BUCK1_RESTART_LEVEL} voltage. Therefore, the LS sink current-limit event is masked when the BUCK1 regulator is enabled, until the BUCK1 output voltage (V_BUCK1) exceeds its UV-threshold level.

1. When the BUCK1 load current continues to increase to greater than the maximum specified load, an UV event can occur.

Figure 11-1 The Wide-VIN BUCK1 Short-Circuit Event