In the operating states (RESET, DIAGNOSTIC, ACTIVE, and SAFE), if a BUCK1 switching-clock error is detected while the internal OSC clock source is in good condition, the following occurs:

• The BUCK1_FSW_CLK_ERR status bit is set.
• the BUCK1 regulator, BUCK2 regulator, and BOOST converter are disabled without enabling resistive discharge.
• The device goes into the SAFE state.
• The device error counter increments.
• The ENDRV/nIRQ pin is asserted low to interrupt the external system MCU.
  Note:

  Eventually, as the BUCK1 regulator, BUCK2 regulator, and BOOST converter discharge to less than the respective UV-threshold level, a global RESET condition is met (as long as one regulator UV event is configured as an NRES source) and the device goes into the RESET state. When the device enters the RESET state, the BUCK1 regulator is enabled again (its default state) only if the SYNC_IN clock monitor and the PLL (or VCO) clock monitor no longer indicates an error, the BUCK1 and BUCK2 regulators are discharged 60% less than the nominal value, and the BOOST converter is discharged below the V_{BOOST_RESTART_LEVEL} voltage value. After the BUCK1 regulator is enabled and the BUCK1 output exceeds its UV-threshold level, the BUCK2 regulator and BOOST converter are enabled.

  All the BUCK1 monitoring and protection mechanisms are active, and if any critical conditions are still present, the BUCK1 regulator is disabled again. If the BUCK1 regulator never recovers while in the RESET state, the RESET state time-out event places the device into the OFF state.

As the rails discharge to less than their UV-threshold level, the device enters the RESET state. While in the RESET state, the switched-mode regulators are enabled by internal start-up control circuit only when none of the DIG_CLK_MONx monitors detect any errors and when the regulator outputs have discharged to less than the V_{BUCKx/BOOST_RESTART_LEVEL} voltage level of the respective target regulation voltage. After the BUCK1 regulator is enabled and the BUCK1 output exceeds its UV-threshold level, the BUCK2 regulator and the BOOST converter are enabled. While in the RESET state, the SYNC_IN clock monitor is disabled, the PLL synchronization to the SYNC_IN clock is stopped and the PLL starts a gradual transition to the free-running VCO clock.