米6体育平台手机版

ZHCSL05C October 2019 – October 2023 TPS65313-Q1

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机械数据 (封装 | 引脚)

RWG|40
- MPQF420

散热焊盘机械数据 (封装 | 引脚)

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11.9.10.5 WD Question and Answer Value Generation

The 4-bit WD question, WD_QUESTION[3:0], is generated by 4-bit Markov chain process. A Markov chain is a stochastic process with Markov property, which means that state changes are probabilistic, and the future state depends only on the current state. The valid and complete WD answer sequence for each WD Q&A mode is as follows:

In WD Q&A multi-answer mode:
1. Three correct SPI WD answers are received during RESPONSE WINDOW 1.
2. One correct SPI WD answer is received during RESPONSE WINDOW 2.
3. In addition to the previously listed timing, the sequence of four responses shall be correct.
In WD Q&A single-answer mode:
1. No SPI WD answer is received during the CLOSE WINDOW.
2. One correct SPI WD answer is received during the OPEN WINDOW.

The WD question value is latched in the WD_QUESTION[3:0] bits of the WDT_QUESTION_VALUE register and can be read out at any time.

If the current y value is 0000, the next y value will be 0001. The next watchdog question generation process starts from that value.

Figure 11-18 Watchdog Question Generation

Table 11-10 Set of WD Questions and Corresponding WD Answers Using Default Setting

QUESTION IN WD_QUESTION_VALUE REGISTER	WD ANSWER BYTES (EACH BYTE TO BE WRITTEN INTO WDT_ANSWER REGISTER)
QUESTION IN WD_QUESTION_VALUE REGISTER	WD_ANSWER_RESP_3	WD_ANSWER_RESP_2	WD_ANSWER_RESP_1⁽¹⁾	WD_ANSWER_RESP_0
WD_QUESTION	WD_ANSW_CNT[1:0] 11b	WD_ANSW_CNT[1:0] 10b	WD_ANSW_CNT[1:0] 01b	WD_ANSW_CNT[1:0] 00b
0x0	0xFF	0x0F	0xF0	0x00
0x1	0xB0	0x40	0xBF	0x4F
0x2	0xE9	0x19	0xE6	0x16
0x3	0xA6	0x56	0xA9	0x59
0x4	0x75	0x85	0x7A	0x8A
0x5	0x3A	0xCA	0x35	0xC5
0x6	0x63	0x93	0x6C	0x9C
0x7	0x2C	0xDC	0x23	0xD3
0x8	0xD2	0x22	0xDD	0x2D
0x9	0x9D	0x6D	0x92	0x62
0xA	0xC4	0x34	0xCB	0x3B
0xB	0x8B	0x7B	0x84	0x74
0xC	0x58	0xA8	0x57	0xA7
0xD	0x17	0xE7	0x18	0xE8
0xE	0x4E	0xBE	0x41	0xB1
0xF	0x01	0xF1	0x0E	0xFE

(1) This option is used for the WD Q&A Single-Answer mode (the WD_CFG bit is set to 1b).

Figure 11-19 WD Expected Answer Generation

Table 11-11 Correct and Incorrect WD Q&A Sequence Run Scenarios for WD Q&A Multi-Answer Mode (WD_CFG = 0b)

NUMBER OF WD ANSWERS		ACTION	WD STATUS BITS IN WDT_STATUS REGISTER				COMMENTS
RESPONSE WINDOW 1	RESPONSE WINDOW 2	ACTION	ANSW_ERR	ANSW_EARLY	SEQ_ERR	TIME_OUT	COMMENTS
0 answer	0 answer	-New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question	0b	0b	1b	1b	No answers
0 answer	4 INCORRECT answer	-New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question	1b	0b	1b	0b	Total WD_ANSW_CNT[1:0] = 4
0 answer	4 CORRECT answer	-New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question	0b	0b	1b	0b	Total WD_ANSW_CNT[1:0] = 4
0 answer	1 CORRECT answer	-New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question	0b	0b	1b	1b	Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 CORRECT ANSWER in RESPONSE WINDOW 2 (Total WD_ANSW_CNT[1:0] < 4)
1 CORRECT answer	1 CORRECT answer
2 CORRECT answer	1 CORRECT answer
0 answer	1 INCORRECT answer	-New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question	1b	0b	1b	1b	Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (Total WD_ANSW_CNT[1:0] < 4)
1 CORRECT answer	1 INCORRECT answer
2 CORRECT answer	1 INCORRECT answer
0 answer	4 CORRECT answer	-New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question	0b	0b	1b	0b	Less than 3 CORRECT ANSWER in WIN1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (Total WD_ANSW_CNT[1:0] = 4)
1 CORRECT answer	3 CORRECT answer
2 CORRECT answer	2 CORRECT answer
0 answer	4 INCORRECT answer	-New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question	1b	0b	1b	0b	Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (Total WD_ANSW_CNT[1:0] = 4)
1 CORRECT answer	3 INCORRECT answer
2 CORRECT answer	2 INCORRECT answer
0 answer	3 CORRECT answer	-New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question	0b	0b	1b	1b	Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (Total WD_ANSW_CNT[1:0] < 4)
1 INCORRECT answer	2 CORRECT answer	-New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question	1b	0b	1b	1b
2 INCORRECT answer	1 CORRECT answer		1b	0b	1b	1b
0 answer	3 INCORRECT answer	-New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question	1b	0b	1b	1b	Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (Total WD_ANSW_CNT[1:0] < 4)
1 INCORRECT answer	2 INCORRECT answer
2 INCORRECT answer	1 INCORRECT answer
0 answer	4 CORRECT answer	-New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question	0b	0b	1b	0b	Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (Total WD_ANSW_CNT[1:0] = 4)
1 INCORRECT answer	3 CORRECT answer		1b	0b	1b	0b
2 INCORRECT answer	2 CORRECT answer		1b	0b	1b	0b
0 answer	4 INCORRECT answer	-New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question	1b	0b	1b	0b	Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (Total WD_ANSW_CNT[1:0] = 4)
1 INCORRECT answer	3 INCORRECT answer
2 INCORRECT answer	2 INCORRECT answer
3 CORRECT answer	0 answer	-New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD Question	0b	0b	0b	1b	Less than 4 CORRECT ANSW in RESPONSE WINDOW 1 and more than 0 ANSWER in RESPONSE WINDOW 2 (Total WD_ANSW_CNT[1:0] < 4)
2 CORRECT answer	0 answer		0b	0b	1b	1b
1 CORRECT answer	0 answer		0b	0b	1b	1b
3 CORRECT answer	1 CORRECT answer	-New WD cycle starts after the 4th WD answer -Decrement WD failure counter -New WD cycle starts with a new WD question	0b	0b	0b	0b	CORRECT SEQUENCE
3 CORRECT answer	1 INCORRECT answer	-New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question	1b	0b	0b	0b	Total WD_ANSW_CNT[1:0] = 4
3 INCORRECT answer	0 answer	-New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question	1b	0b	0b	1b	Total WD_ANSW_CNT[1:0] < 4
3 INCORRECT answer	1 CORRECT answer	-New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question	1b	0b	0b	0b	Total WD_ANSW_CNT[1:0] = 4
3 INCORRECT answer	1 INCORRECT answer	-New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question	1b	0b	0b	0b	Total WD_ANSW_CNT[1:0] = 4
4 CORRECT answer	Not applicable	-New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question	0b	1b	0b	0b
3 CORRECT answer + 1 INCORRECT answer	Not applicable	-New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question	1b	1b	0b	0b	4 CORRECT or INCORRECT ANSWER in RESPONSE WINDOW 1
2 CORRECT answer + 2 NCORRECT answer	Not applicable
1 CORRECT answer + 3 NCORRECT answer	Not applicable

Table 11-12 Correct and Incorrect WD Q&A Sequence Run Scenarios for WD Q&A Single-Answer Mode

NUMBER OF WD ANSWERS AND TIMING		ACTION	WD STATUS BITS IN WDT_STATUS REGISTER
CLOSE WINDOW	OPEN WINDOW	ACTION	ANSW_ERR	ANSW_EARLY	SEQ_ERR	TIME_OUT
0 answer	0 answer	-New WD cycle starts after the end of WIN2 -Increment WD failure counter -New WD cycle starts with the same WD question	0b	0b	0b	1b
1 CORRECT answer	0 answer	-New WD cycle starts after the end of RESPONSE WINDOW 1 -Increment WD failure counter -New WD cycle starts with the same WD question	0b	1b	0b	0b
1 INCORRECT answer	0 answer	-New WD cycle starts after the end of RESPONSE WINDOW 1 -Increment WD failure counter -New WD cycle starts with the same WD question	1b	1b	0b	0b
0 answer	1 CORRECT answer	-New WD cycle starts after the end of RESPONSE WINDOW 2 -Decrement WD failure counter -New WD cycle starts with the same WD question	0b	0b	0b	0b
0 answer	1 INCORRECT answer	-New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question	1b	0b	0b	0b

The watchdog status bits (ANSW_ERR, ANSW_EARLY, SEQ_ERR, and TIME_OUT) in the WDT_STATUS register are updated at the end of each WD cycle. Read access to the WDT_STATUS register during an active WD cycle returns the status of previous WD cycle and clears the WD status bits.