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ZHCSL05C October 2019 – October 2023 TPS65313-Q1

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11.9.5 Logic Built-In Self-Test

The logic built-in self-test (LBIST) tests the following monitoring and protection circuits in the digital core:

The digital clock monitors (DIG_CLK_MON1, DIG_CLK_MON2, DIG_CLK_MON3, DIG_CLK_MON4, DIG_CLK_MON5, and DIG_CLK_MON6)
The watchdog
The MCU error signal monitor
The ENDRV/nIRQ pin error detector
The NRES pin error detector
The SPI status registers
The EEPROM controller
The ABIST controller
The SPI controller
The deglitch circuits

The digital core LBIST implementation is using an at-speed capture cycle with a run time of approximately 1.7 ms.

In case of an LBIST failure, the device goes into the SAFE state, and the LBIST_CORE_ERR bit in the SAFETY_LBIST_ERR_STAT register is set.

The LBIST runs in the RESET state when the RESET state extension is in progress. The LBIST can also run in the other operating states by setting the LBIST_EN bit, if the system fault-response time can allow the total 1.7 ms (typical) of run time to occur. During the LBIST, the device cannot monitor the supply outputs or the system MCU with the ESM and the watchdog. When the LBIST is complete, the LBIST_DONE status bit is set and the LBIST_EN control bit in the SAFETY_LBIST_CTRL register is cleared.

When the LBIST is activated in the DIAGNOSTIC state, the device clears the DIAG_EXIT_MASK bit in the DEV_STAT2 register. The DIAGNOSTIC state time-out timer continues to run while the LBIST is in progress. To keep the device in the DIAGNOSTIC state, the system MCU must set the DIAG_EXIT_MASK bit after the LBIST completion.

When the LBIST is activated while the device is in the ACTIVE state or the SAFE state, the state of the ENDRV/nIRQ driver is latched. The state of the ENDRV/nIRQ drive is restored when the LBIST is complete.

The diagnostic test on the LBIST can run by setting the LBIST_DIAG_EN control bit. The test on the LBIST signature check is performed by modifying either the expected signature value, input data string modification or both to force an LBIST error. The LBIST_DIAG_EN bit is cleared when the LBIST diagnostic test is complete.

The Table 11-3 summarizes the consequences of the LBIST runs.

Table 11-3 LBIST Control and Status

LBIST_EN⁽³⁾	LBIST_DIAG_EN⁽³⁾	LBIST_DONE ⁽⁴⁾	LBIST_CORE_ERR	LBIST_DIAG_ERR	DEVICE STATE
0b	0b	No change	No change	No change	No state change
0b	1b	1b	No change	0⁽¹⁾	No state change
0b	1b	1b	No change	1b	SAFE
1b	0b	1b	0b⁽²⁾	No change	No state change
1b	0b	1b	1b	No change	SAFE

(1) This value assumes that the LBIST_DIAG_ERR bit was set to 0b prior to setting the LBIST_DIAG_EN bit.

(2) This value assumes that the LBIST_CORE_ERR bit was set to 0b prior to setting the LBIST_EN bit.

(3) TI does not recommended setting both the LBIST_EN and LBIST_DIAG_EN bits at the same time. In this case, the LBIST_DIAG_EN bit setting has higher priority.

(4) If the system MCU keeps polling the LBIST_DONE status bit while the LBIST is in progress, the bit reads 0b until the LBIST is complete and until the SPI communication is restored. However, the first read command after the LBIST completion can generate a SPI format error, which is noted by the SPI_ERR[1:0] bit when set to 10b at the next read command. The LBIST_DONE bit is then the accurate representation of the LBIST status during this same SPI read command. TI recommends that the MCU read the bit again and confirm the bit is cleared back to 0b.