米6体育平台手机版

ZHCSL05C October 2019 – October 2023 TPS65313-Q1

PRODUCTION DATA

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机械数据 (封装 | 引脚)

RWG|40
- MPQF420

散热焊盘机械数据 (封装 | 引脚)

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11.9.10.2 WD Failure Counter and WD Status

The WD function uses a WD failure counter (WD_FAIL_CNT[3:0]) to track correct and incorrect MCU answers. The WD_FAIL_CNT[3:0] counter increments for each incorrect answer and decrements for each correct answer.

The WD_FAIL_CNT[3:0] counter is updated by the following events when the device is in the DIAGNOSTIC or ACTIVE or SAFE state:

A correct WD answer decrements the WD_FAIL_CNT[3:0] counter by 1.
A wrong WD answer increments the WD_FAIL_CNT[3:0] counter by 1.
An incomplete or missing WD answer for the duration of the programmed WD sequence duration (or WD time-out event) increments the WD_FAIL_CNT[3:0] counter by 1 and sets the TIME_OUT status bit in the WDT_STATUS register.
Any change in the WD_CFG bit, WD window time durations (WDT_WIN1_CFG or WDT_WIN2_CFG register), or WD answer generation configurations (WDT_QA_CFG register) increments the WD_FAIL_CNT[3:0] counter by 1.

When the value of the WD_FAIL_CNT[3:0] counter is less than the value set by the WD_FC_ENDRV_TH[3:0] bits, the WD function is considered to be in range, and the device keeps the WD-enabled function active (the ENDRV/nIRQ driver can be activated and the ENDRV/nIRQ pin is pulled high). The WD-enabled function is enabled by setting the ENDRV_EN control bit in the SAFETY_CHECK_CTRL register. When the value of the WD_FAIL_CNT[3:0] counter is greater than the value set by the WD_FC_ENDRV_TH[3:0] bits in the SAFETY_CFG4 register, the WD function is considered to be out of range, and the device disables the WD-enabled ENDRV/nIRQ function by driving ENDRV/nIRQ pin low. Figure 11-15 summarizes the settings of the WD status bits depending on the WD_FAIL_CNT[3:0] counter value with respect to the WD_FC_ENDRV_TH[3:0] bits value.

When the condition is met, the device goes from the ACTIVE or DIAGNOSTIC state to the SAFE state. No action occurs if the device is in the SAFE state.
When the condition is met, the device stays in the ACTIVE state if the MCU_ESM_RST_EN bit is 0b. When the condition is met, the device goes from the ACTIVE or DIAGNOSTIC state to the RESET state if the MCU_ESM_RST_EN bit is 1b
When the condition is met, the device does not go from the ACTIVE or DIAGNOSTIC state to the SAFE state.
When the condition is met, the device goes from the ACTIVE or DIAGNOSTIC state to the SAFE state.

Figure 11-15 Watchdog Impact on ENDRV/nIRQ Output Function

Table 11-8 WD Fail Counter Ranges for ENDRV Function

WD STATUS BITS	WD_FAIL_CNT[3:0] = 0b	0b < WD_FAIL_CNT[3:0] < WD_FC_ENDRV_TH[3:0]⁽²⁾	WD_FAIL_CNT[3:0] ≥ WD_FC_ENDRV_TH[3:0]⁽³⁾
WD_FAIL⁽¹⁾	0b	1b	1b
WD_ENDRV_FAIL	0b	0b	1b

(1) The WD_FAIL status bit is set each time the WD_FAIL_CNT[3:0] counter increments.

(2) The WD is in range.

(3) The WD is out of range.

If the WD_RST_EN configuration bit in the SAFETY_CFG3 register is set to 1b, the WD generates a reset to the MCU by driving NRES pin low when the WD_FAIL_CNT[3:0] counter reaches the programmed threshold set by the WD_FC_RST_TH[3:0] bits. Table 11-9 summarizes the WD status bits and device state depending on the WD_FAIL_CNT[3:0] counter value with respect to WD_FC_RST_TH[3:0] bits value.

Table 11-9 WD Fail Counter Ranges for WD Reset

WD STATUS BITS	WD_FAIL_CNT[3:0] = 0b	0b < WD_FAIL_CNT[3:0] < WD_FC_RST_TH[3:0]⁽²⁾	WD_FAIL_CNT[3:0] = WD_FC_RST_TH[3:0] and WD_RST_EN = 1b⁽³⁾	WD_FAIL_CNT[3:0] = WD_FC_RST_TH[3:0] and WD_RST_EN = 0b⁽³⁾
WD_FAIL⁽¹⁾	0b	1b	1b	1b
WD_RST_FAIL	0b	0b	1b	1b
Device State	No change	No change	RESET state ⁽⁴⁾	SAFE state

(1) The WD_FAIL status bit is set each time the WD_FAIL_CNT[3:0] increments.

(2) The WD is in range.

(3) The WD is out of range.

(4) When device was in DIAGNOSTIC or ACTIVE state, or device was in SAFE state and SAFE_EXIT SPI command is received.

When a NPOR event occurs, the WD_FAIL_CNT[3:0] counter is initialized to 0x05, which is the initial value of the WD_FC_ENDRV_TH[3:0] bits. While the device is in the DIAGNOSTIC state, the MCU can set the desired WD_FC_ENDRV_TH[3:0] and WD_FC_RST_TH[3:0] values. Setting new WD_FC_ENDRV_TH[3:0] value in DIAGNOSTIC state causes the WD_FAIL_CNT[3:0] counter to be set to the same new value. This WD_FAIL_CNT[3:0] bits update is to make sure that the ENDRV function is initially disabled until correct WD answers are provided by the MCU.

When the WD_FAIL_CNT[3:0] counter reaches a count of 0xF, any new incorrect answer from the MCU does not change the counter value. The counter stays at 0xF. Similarly, when the WD_FAIL_CNT[3:0] counter reaches a count of 0x0, any new correct WD answers do not change the counter value. The counter stays at 0x0.