The SYNC_IN pin can be used as the external clock input. This input pin requires a 2.2-MHz (typ) clock with a low level less than 0.4 V, a high level more than 2 V, and a duty cycle from 10% to 90%. If the device does not detect any clock on the SYNC_IN pin, then the regulators get a clock from the free-running VCO in the PLL.