ZHCSL05C October   2019  – October 2023 TPS65313-Q1

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. 器件功能方框图
  6. Revision History
  7. 说明(续)
  8. Device Option Table
  9. Pin Configuration and Functions
  10. Specifications
    1. 9.1  Absolute Maximum Ratings
    2. 9.2  ESD Ratings
    3. 9.3  Recommended Operating Conditions
    4. 9.4  Thermal Information
    5. 9.5  Power-On-Reset, Current Consumption, and State Timeout Characteristics
    6. 9.6  PLL/Oscillator and SYNC_IN Pin Characteristics
    7. 9.7  Wide-VIN Synchronous Buck Regulator (Wide-VIN BUCK) Characteristics
    8. 9.8  Low-Voltage Synchronous Buck Regulator (LV BUCK) Characteristics
    9. 9.9  Synchronous Boost Converter (BOOST) Characteristics
    10. 9.10 Internal Voltage Regulator (VREG) Characteristics
    11. 9.11 Voltage Monitors for Regulators Characteristics
    12. 9.12 External General Purpose Voltage Monitor Characteristics
    13. 9.13 VIN and VIN_SAFE Under-Voltage and Over-Voltage Warning Characteristics
    14. 9.14 WAKE Input Characteristics
    15. 9.15 NRES (nRESET) Output Characteristics
    16. 9.16 ENDRV/nIRQ Output Characteristics
    17. 9.17 Analog DIAG_OUT
    18. 9.18 Digital INPUT/OUTPUT IOs (SPI Interface IOs, DIAG_OUT/SYNC_OUT, MCU_ERROR)
    19. 9.19 BUCK1, BUCK2, BOOST Thermal Shutdown / Over Temperature Protection Characteristics
    20. 9.20 PGNDx Loss Detection Characteristics
    21. 9.21 SPI Timing Requirements
    22. 9.22 SPI Characteristics
    23. 9.23 Typical Characteristics
  11. 10Parameter Measurement Information
  12. 11Detailed Description
    1. 11.1  Overview
    2. 11.2  Functional Block Diagram
    3. 11.3  Wide-VIN Buck Regulator (BUCK1)
      1. 11.3.1 Fixed-Frequency Voltage-Mode Step-Down Regulator
      2. 11.3.2 Operation
      3. 11.3.3 Voltage Monitoring (Monitoring and Protection)
      4. 11.3.4 Overcurrent Protection (Monitoring and Protection)
      5. 11.3.5 Thermal Warning and Shutdown Protection (Monitoring and Protection)
      6. 11.3.6 Overvoltage Protection (OVP) (Monitoring and Protection)
      7. 11.3.7 Extreme Overvoltage Protection (EOVP) (Monitoring and Protection)
    4. 11.4  Low-Voltage Buck Regulator (BUCK2)
      1. 11.4.1 Fixed-Frequency Peak-Current Mode Step-Down Regulator
      2. 11.4.2 Operation
      3. 11.4.3 Output Voltage Monitoring (Monitoring and Protection)
      4. 11.4.4 Overcurrent Protection (Monitoring and Protection)
      5. 11.4.5 Thermal Sensor Warning and Thermal Shutdown Protection (Monitoring and Protection)
      6. 11.4.6 Overvoltage Protection (OVP) (Monitoring and Protection)
    5. 11.5  Low-Voltage Boost Converter (BOOST)
      1. 11.5.1 Output Voltage Monitoring (Monitoring and Protection)
      2. 11.5.2 Overcurrent Protection (Monitoring and Protection)
      3. 11.5.3 Thermal Sensor Warning and Shutdown Protection (Monitoring and Protection)
      4. 11.5.4 Overvoltage Protection (OVP) (Monitoring and Protection)
    6. 11.6  VREG Regulator
    7. 11.7  BUCK1, BUCK2, and BOOST Switching Clocks and Synchronization (SYNC_IN) Clock
      1. 11.7.1 Internal fSW Clock Configuration (fSW Derived from an Internal Oscillator)
      2. 11.7.2 BUCK1 Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      3. 11.7.3 BUCK2 Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      4. 11.7.4 BOOST Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      5. 11.7.5 External fSW Clock Configuration (fSW Derived from SYNC_IN and PLL Clocks)
        1. 11.7.5.1 SYNC_IN, PLL, and VCO Clock Monitors
        2. 11.7.5.2 BUCK1 Switching Clock-Monitor Error (External fSW Clock Configuration)
        3. 11.7.5.3 BUCK2 Switching Clock-Monitor Error (External fSW Clock Configuration)
        4. 11.7.5.4 BOOST Switching Clock-Monitor Error (External fSW Clock Configuration)
    8. 11.8  BUCK1, BUCK2, and BOOST Switching-Clock Spread-Spectrum Modulation
    9. 11.9  Monitoring, Protection and Diagnostics Overview
      1. 11.9.1  Safety Functions and Diagnostic Overview
      2. 11.9.2  Supply Voltage Monitor (VMON)
      3. 11.9.3  Clock Monitors
      4. 11.9.4  Analog Built-In Self-Test
        1. 11.9.4.1 ABIST During Power-Up or Start-Up Event
        2. 11.9.4.2 ABIST in the RESET state
        3. 11.9.4.3 ABIST in the DIAGNOSTIC, ACTIVE, and SAFE State
        4. 11.9.4.4 ABIST Scheduler in the ACTIVE State
      5. 11.9.5  Logic Built-In Self-Test
      6. 11.9.6  Junction Temperature Monitors
      7. 11.9.7  Current Limit
      8. 11.9.8  Loss of Ground (GND)
      9. 11.9.9  Diagnostic Output Pin (DIAG_OUT)
        1. 11.9.9.1 Analog MUX Mode on DIAG_OUT
        2. 11.9.9.2 Digital MUX Mode on DIAG_OUT
          1. 11.9.9.2.1 MUX-Output Control Mode
          2. 11.9.9.2.2 Device Interconnect Mode
      10. 11.9.10 Watchdog
        1. 11.9.10.1 WD Question and Answer Configurations
        2. 11.9.10.2 WD Failure Counter and WD Status
        3. 11.9.10.3 WD SPI Event Definitions
        4. 11.9.10.4 WD Q&A Sequence Run
        5. 11.9.10.5 WD Question and Answer Value Generation
          1. 11.9.10.5.1 WD Initialization Events
      11. 11.9.11 MCU Error Signal Monitor
      12. 11.9.12 NRES Driver
      13. 11.9.13 ENDRV/nIRQ Driver
      14. 11.9.14 CRC Protection for the Device Configuration Registers
      15. 11.9.15 CRC Protection for the Device EEPROM Registers
    10. 11.10 General-Purpose External Supply Voltage Monitors
    11. 11.11 Analog Wake-up and Failure Latch
    12. 11.12 Power-Up and Power-Down Sequences
    13. 11.13 Device Fail-Safe State Controller (Monitoring and Protection)
      1. 11.13.1 OFF State
      2. 11.13.2 INIT State
      3. 11.13.3 RESET State (ON Transition From the INIT State)
      4. 11.13.4 RESET State (ON Transition From DIAGNOSTIC, ACTIVE, and SAFE State)
      5. 11.13.5 DIAGNOSTIC State
      6. 11.13.6 ACTIVE State
      7. 11.13.7 SAFE State
      8. 11.13.8 State Transition Priorities
    14. 11.14 Wakeup
    15. 11.15 Serial Peripheral Interface (SPI)
      1. 11.15.1 SPI Command Transfer Phase
      2. 11.15.2 SPI Data Transfer Phase
      3. 11.15.3 Device SPI Status Flag Response Byte
      4. 11.15.4 Device SPI Data Response
      5. 11.15.5 Device SPI Master CRC (MCRC) Input
      6. 11.15.6 Device SPI Slave CRC (SCRC) Output
      7. 11.15.7 SPI Frame Overview
    16. 11.16 Register Maps
      1. 11.16.1 Device SPI Mapped Registers
        1. 11.16.1.1 Memory Maps
          1. 11.16.1.1.1 SPI Registers
  13. 12Applications, Implementation, and Layout
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
      2. 12.2.2 Detailed Design Procedure
        1. 12.2.2.1  Selecting the BUCK1, BUCK2, and BOOST Output Voltages
        2. 12.2.2.2  Selecting the BUCK1, BUCK2, and BOOST Inductors
        3. 12.2.2.3  Selecting the BUCK1 and BUCK2 Output Capacitors
        4. 12.2.2.4  Selecting the BOOST Output Capacitors
        5. 12.2.2.5  Input Filter Capacitor Selection for BUCK1, BUCK2, and BOOST
        6. 12.2.2.6  Input Filter Capacitors on AVIN and VIN_SAFE Pins
        7. 12.2.2.7  Bootstrap Capacitor Selection
        8. 12.2.2.8  Internal Linear Regulator (VREG) Output Capacitor Selection
        9. 12.2.2.9  EXTSUP Pin
        10. 12.2.2.10 WAKE Input Pin
        11. 12.2.2.11 VIO Supply Pin
        12. 12.2.2.12 External General-Purpose Voltage Monitor Input Pins (EXT_VSENSE1 and EXT_VSENSE2)
        13. 12.2.2.13 SYNC_IN Pin
        14. 12.2.2.14 MCU_ERR Pin
        15. 12.2.2.15 NRES Pin
        16. 12.2.2.16 ENDRV/nIRQ Pin
        17. 12.2.2.17 DIAG_OUT Pin
        18. 12.2.2.18 SPI Pins (NCS,SCK, SDI, SDO)
        19. 12.2.2.19 PBKGx, AGND, DGND, and PGNDx Pins
        20. 12.2.2.20 Calculations for Power Dissipation and Junction Temperature
          1. 12.2.2.20.1 BUCK1 Output Current Calculation
          2. 12.2.2.20.2 Device Power Dissipation Estimation
          3. 12.2.2.20.3 Device Junction Temperature Estimation
            1. 12.2.2.20.3.1 Example for Device Junction Temperature Estimation
      3. 12.2.3 Application Curves
      4. 12.2.4 Layout
        1. 12.2.4.1 Layout Guidelines
        2. 12.2.4.2 Layout Example
        3. 12.2.4.3 Considerations for Board-Level Reliability (BLR)
    3. 12.3 Power Supply Coupling and Bulk Capacitors
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 接收文档更新通知
    3. 13.3 支持资源
    4. 13.4 Trademarks
    5. 13.5 静电放电警告
    6. 13.6 术语表
  15. 14Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Application Curves

These parameters are not tested and represent typical performance only. Unless otherwise stated, the following conditions apply: VIN = 13 V, TA = 25°C, Spread Spectrum Modulation (SSM) Disabled, external components mentioned in Section 12.2.

GUID-6A61D0DE-6FCB-4C26-BF47-FD507578B2C7-low.gif
Note:
VBUCK1 = 3.3 V
Figure 12-2 BUCK1 Efficiency
GUID-69944F10-2AE3-49B6-AE32-D3AD03FD7224-low.gif
Note:
VBUCK1 = 3.3 V VIN = 13 V
Figure 12-4 BUCK1 Efficiency
GUID-0313040F-1B42-4B93-A0A4-0E7B42A53865-low.gif
Note:
VBUCK1 = 3.3 V LOUT = IHLP2525CZER1R0M5A
Figure 12-6 BUCK2 Efficiency
GUID-0C43E216-F2F6-46EE-A27A-413E56EA853C-low.gif
Note:
VBUCK1 = 3.3 V VBUCK2 = 1.8 V
LOUT = IHLP2525CZER1R0M5A
Figure 12-8 BUCK2 Efficiency
GUID-144CE8BA-8895-4BB0-8CFF-2B085BB2DE77-low.gif
Note:
VBUCK1 = 3.3 V LOUT = IHLP2525CZER1R5M5A
Figure 12-10 BOOST Efficiency
GUID-0E5103A0-A903-45D8-8670-93BC0270CFFE-low.gif
Note:
VBUCK1 = 3.6 V
Figure 12-12 BUCK1 Load and Line Regulation
GUID-CF37113F-9192-4672-B23D-5151F615424C-low.gif
Note:
VBUCK1 = 3.3 V
Figure 12-14 BUCK1 Load Regulation
GUID-C1282CAB-9CDF-402C-9BCC-B7B1FE920F9E-low.gif
Note:
VBUCK2 = 1.8 V COUT = 22 µF + 10 µF
LOUT = IHLP2525CZER1R0M5A
Figure 12-16 BUCK2 Load Regulation
GUID-8C752D5B-B4AA-4EBA-B235-6A1D8EA17D85-low.gif
Note:
VBUCK2 = 1.8 V COUT = 22 µF + 10 µF
VBUCK1 = 3.3 V LOUT = IHLP2525CZER1R0M5A
Figure 12-18 BUCK2 Load Regulation
GUID-A7969C76-05B7-4C00-A866-539AE61D6E5A-low.gif
Note:
VBUCK1 = 3.3 V COUT = 22 µF + 10 µF
LOUT = IHLP2525CZER1R5M5A
Figure 12-20 BOOST Load Regulation
GUID-3327E32B-82FB-453A-9A1A-3084B02B2D56-low.gif
Note:
VOUT (VBUCK1) = 3.6 V TR = TF = 1 µs
IOUT = 0 A to 2 A
Figure 12-22 BUCK1 Load Transient
GUID-301E326F-6F6E-426B-AA1A-FB683F310B9A-low.gif
Note:
VOUT (VBUCK2) = 1.8 V TR = TF = 1 µs
VBUCK1 = 3.3 V IOUT = 0 A to 1 A
Figure 12-24 BUCK2 Load Transient
GUID-03D765F1-FDE2-4755-90F0-3A818009FB4E-low.gif
Note:
VOUT (VBUCK2) = 1.2 V TR = TF = 1 µs
VBUCK1 = 3.6 V IOUT = 0 A to 1 A
Figure 12-26 BUCK2 Load Transient
GUID-022F7913-5301-4924-BFDD-497E5F30811D-low.gif
Note:
VOUT (VBUCK2) = 2.3 V TR = TF = 1 µs
VBUCK1 = 3.6 V IOUT = 0 A to 1 A
Figure 12-28 BUCK2 Load Transient
GUID-1CA5EDEC-6866-46BE-B5FA-B4AC9D7F14C4-low.gif
Note:
VOUT (VBOOST) = 5 V TR = TF = 1 µs
VBUCK1 = 3.6 V IOUT = 0 A to 0.6 A
Figure 12-30 BOOST Load Transient
GUID-2EF4BA7B-2A09-4A61-942E-690D3645A8D3-low.gif
Note:
VOUT (VBUCK1) = 3.6 V IOUT = 3.1 A
Figure 12-32 BUCK1 Output Voltage Ripple
GUID-811C2C8C-5417-4691-9407-0D0B510AA0AF-low.gif
Note:
VOUT (VBUCK2) = 1.2 V VBUCK1 = 3.3 V IOUT = 2 A
Figure 12-34 BUCK2 Output Voltage Ripple
GUID-53DE5092-88A7-475B-A739-8751E6FF3B43-low.gif
Note:
VOUT (VBUCK2) = 2.3 V VBUCK1 = 3.3 V IOUT = 1.5 A
Figure 12-36 BUCK2 Output Voltage Ripple
GUID-ED4DCFCD-09B4-47A5-B76E-615240A717CD-low.gif
Note:
VOUT (VBUCK2) = 1.8 V SSM Enabled IOUT = 2 A
VBUCK1 = 3.3 V
Figure 12-38 BUCK2 Output Voltage Ripple
GUID-8681585A-93BF-4427-AE90-275DB5CD3A4C-low.gif
Note:
VOUT (VBOOST) = 5 V VBUCK1 = 3.6 V IOUT = 0.6 A
Figure 12-40 BOOST Output Voltage Ripple
GUID-512C5682-8C01-4962-90D6-DF1DFADFC6ED-low.gif
Note:
Figure 12-42 Start-up With VIN and WAKE Connected Together
GUID-8A9110DF-B5DD-4266-9EE6-F58018F08EF6-low.png
Figure 12-44 Start-up Showing NRES Output With Short NRES Extension Delay
GUID-6EFF08C9-A748-4244-A102-0E781D6DC406-low.gifFigure 12-46 Shutdown Showing NRES Output
GUID-8FBE3611-14C9-41AF-A421-138642A86B81-low.gif
Note:
VBUCK1 = 3.6 V
Figure 12-3 BUCK1 Efficiency
GUID-9C8988CB-9386-4460-AAC1-4AA5B341ED5E-low.gif
Figure 12-5 BUCK1 Output Current at Low VIN Conditions
GUID-2B5C738A-7610-43A9-A730-728D6F6B9F0D-low.gif
Note:
VBUCK1 = 3.6 V LOUT = IHLP2525CZER1R0M5A
Figure 12-7 BUCK2 Efficiency
GUID-57783575-DEE7-4BF1-AF7A-0A1E684FED52-low.gif
Note:
LOUT = IHLP2525CZER1R5M5A
Figure 12-9 BOOST Efficiency
GUID-51A5D0B5-80D2-4FC7-A6FF-E777A82F4D6F-low.gif
Note:
VBUCK1 = 3.3 V
Figure 12-11 BUCK1 Load and Line Regulation
GUID-E2AA242A-4B86-4FB1-A7C9-73FE19DA81C3-low.gif
Note:
VBUCK1 = 3.3 V IOUT= 2 A
Figure 12-13 BUCK1 Line Regulation
GUID-AE98CCE9-00EA-4944-AB4F-A1570FF11B97-low.gif
Note:
VBUCK2 = 1.2 V COUT = 22 µF + 10 µF
LOUT = IHLP2525CZER1R0M5A
Figure 12-15 BUCK2 Load Regulation
GUID-29487C97-6325-4336-B393-20A3D52348A5-low.gif
Note:
VBUCK2 = 2.3 V COUT = 22 µF + 10 µF
LOUT = IHLP2525CZER1R0M5A
Figure 12-17 BUCK2 Load Regulation
GUID-1DA6A9B2-34F8-4695-8818-7D59FC1C4427-low.gif
Note:
COUT = 22 µF + 10 µF LOUT = IHLP2525CZER1R5M5A
Figure 12-19 BOOST Load and Line Regulation
GUID-F91B3873-3208-40FE-9E42-93382954FF0B-low.gif
Note:
VOUT (VBUCK1) = 3.3 V TR = TF = 1 µs
IOUT = 0 A to 2 A
Figure 12-21 BUCK1 Load Transient
GUID-61D37D1B-DFF7-4804-9047-3F56DBDAF896-low.gif
Note:
VOUT (VBUCK2) = 1.2 V TR = TF = 1 µs
VBUCK1 = 3.3 V IOUT = 0 A to 1 A
Figure 12-23 BUCK2 Load Transient
GUID-BCFB1CF4-03D0-4649-88F1-3C655F77FCFE-low.gif
Note:
VOUT (VBUCK2) = 2.3 V TR = TF = 1 µs
VBUCK1 = 3.3 V IOUT = 0 A to 1 A
Figure 12-25 BUCK2 Load Transient
GUID-36BF6C03-5541-44F4-8017-9DF5111741C8-low.gif
Note:
VOUT (VBUCK2) = 1.8 V TR = TF = 1 µs
VBUCK1 = 3.6 V IOUT = 0 A to 1 A
Figure 12-27 BUCK2 Load Transient
GUID-E3E18347-AD9A-4821-B2A8-194337A062F2-low.gif
Note:
VOUT (VBOOST) = 5 V TR = TF = 1 µs
VBUCK1 = 3.3 V IOUT = 0 A to 0.6 A
Figure 12-29 BOOST Load Transient
GUID-14D6CF62-5CAB-4153-8BD1-71AFE26C1BA5-low.gif
Note:
VOUT (VBUCK1) = 3.3 V IOUT = 3.1 A
Figure 12-31 BUCK1 Output Voltage Ripple
GUID-71575868-971C-4556-B14B-9B4CD5C81056-low.gif
Note:
VOUT (VBUCK1) = 3.3 V SSM Enabled IOUT = 3.1 A
Figure 12-33 BUCK1 Output Voltage Ripple
GUID-7A28EC2F-7D00-4EE8-B18B-801A03773820-low.gif
Note:
VOUT (VBUCK2) = 1.8 V VBUCK1 = 3.3 V IOUT = 2 A
Figure 12-35 BUCK2 Output Voltage Ripple
GUID-144718D1-A2D4-4535-AFD0-3428ACFD1673-low.gif
Note:
VOUT (VBUCK2) = 1.8 V VBUCK1 = 3.6 V IOUT = 2 A
Figure 12-37 BUCK2 Output Voltage Ripple
GUID-3DF91C4A-3DF7-42AD-9F80-04AAA7A98F43-low.gif
Note:
VOUT (VBOOST) = 5 V VBUCK1 = 3.3 V IOUT = 0.6 A
Figure 12-39 BOOST Output Voltage Ripple
GUID-3578AC7A-01CE-4A8D-8914-525CE8E77030-low.gif
Note:
VOUT (VBOOST) = 5 V SSM Enabled IOUT = 0.6 A
VBUCK1 = 3.3 V
Figure 12-41 BOOST Output Voltage Ripple
GUID-43B01C6B-C08A-4ABC-A241-9212129DD51A-low.png
Note:
Figure 12-43 Start-up Showing NRES Output With Long NRES Extension Delay
GUID-E0C2A4F5-375F-42D4-8927-C4D2010BDF2B-low.gif
Note:
Figure 12-45 Shutdown With VIN