ZHCSL05C October 2019 – October 2023 TPS65313-Q1
PRODUCTION DATA
The supply voltage monitor (VMON) monitors the device supply voltage, all regulator output voltages, the internal regulators, and up to two external supply rails. The SPI register has VMON status bits (UV, OV, and OVP) to indicate an undervoltage or overvoltage event (error event) for each monitored voltage rail. The device keeps the VMON status bits set to 0b during the ramp up of the monitored rails. The device sets the status bit to 1b when the monitored rail is outside the specified range. The status bit stays set until it is cleared by a valid SPI read command if the corresponding fault condition is removed.
The complete VMON block is supplied by a separate supply pin (VIN_SAFE). The reference voltages for the VMON module (VREF_MON) are derived from a redundant band-gap reference (BG2) which is independent of the primary band-gap reference (BG1). BG1 provides reference voltages (VREF_REG) for the regulators and other functional blocks. The VMON module has a deglitch timer for each monitored supply rail. If the error event occurs for a time period shorter than the deglitch time, the VMON module does not set the corresponding VMON status bit. The device keeps the VMON status bits set to 0b during the ramp up of the monitored voltage rails to make sure monitoring is reliable without false setting of the VMON status bits. When the device is in the operating states, the voltage monitoring is continuous and stays active even after the respective regulator has been disabled.
The analog-built-in self-test (ABIST) runs the VMON modules' diagnostic check. The ABIST is executed during device power-up or when activated by the system MCU when the device is in the DIAGNOSTIC, ACTIVE, or SAFE state. Each monitored voltage rail is emulated for an undervoltage, overvoltage, and overvoltage protection condition on the corresponding comparator inputs which forces the corresponding comparator to toggle multiple times. The comparator output toggling pattern is observed and checked by the ABIST digital controller. The monitored voltage rails are not affected during the ABIST. No undervoltage or overvoltage events occur on any of monitored rails because of these diagnostic tests.
Table 11-1 provides an overview of the voltage monitoring.
| VOLTAGE RAIL | MONITORED PIN | DETECTION THRESHOLD RANGE | DEGLITCH TIME | DEVICE BEHAVIOR UPON DETECTION (SPI FLAG, STATE TRANSITION, NRES/ENDRV PIN STATUS) | ABIST | |||||
|---|---|---|---|---|---|---|---|---|---|---|
| UV | OV | OVP | UV/OV | OVP | UV | OV | OVP | |||
| VBAT | AVIN | 5.8 V to 6.6 V(1) | 36 V to 40 V | — | UV: 90 µs to 110 µs OV: 10 µs to 20 µs |
— | VMON_UV_STAT[6] No change in state No change in NRES, ENDRV/nIRQ = 0 if VIN_BAD_IRQ_EN = 1(2) |
VMON_OV_STAT[6] OFF state NRES = 0, ENDRV/nIRQ = 0 |
— | NO |
| VBUCK1(3) | VSENSE1 | –5.0% to –2.5% | 2.5% to 5.0% | 6% to 10% | 21 µs to 39 µs | 21 µs to 39 µs | VMON_UV_STAT[0] RESET state if BUCK1_UV_RST_EN = 1, SAFE state if BUCK1_UV_RST_EN = 0 NRES = 0, ENDRV/nIRQ = 0 if BUCK1_UV_RST_EN = 1, NRES = 1, ENDRV/nIRQ = 0 if BUCK1_UV_RST_EN = 0 |
VMON_OV_STAT[0] RESET state if BUCK1_OV_RST_EN = 1, SAFE state if BUCK1_OV_RST_EN = 0 NRES = 0, ENDRV/nIRQ = 0 if BUCK1_OV_RST_EN = 1, NRES = 1, ENDRV/nIRQ = 0 if BUCK1_OV_RST_EN = 0 |
SAFETY_BUCK1_STAT1[3] OFF state if BUCK1_OVP_OFF_EN = 1, SAFE state if BUCK1_OVP_OFF_EN = 0 NRES = 0, ENDRV/nIRQ = 0 if BUCK1_OVP_OFF_EN = 1, NRES = 1, ENDRV/nIRQ = 0 if BUCK1_OVP_OFF_EN = 0 |
YES |
| VBUCK2 | VSENSE2 | –5.0% to –2.5% | 2.5% to 5.0% | 6% to 10% | 21 µs to 39 µs | 21 µs to 39 µs | VMON_UV_STAT[1] RESET state if BUCK2_UV_RST_EN = 1, No state change if BUCK2_UV_RST_EN = 0 NRES = 0, ENDRV/nIRQ = 0 if BUCK2_UV_RST_EN = 1, NRES = 1, ENDRV/nIRQ = 0 if BUCK2_UV_RST_EN = 0 |
VMON_OV_STAT[1] RESET state if BUCK2_OV_RST_EN = 1, SAFE state if BUCK2_OV_RST_EN = 0 NRES = 0, ENDRV/nIRQ = 0 if BUCK1_OV_RST_EN = 1, NRES = 1, ENDRV/nIRQ = 0 if BUCK2_OV_RST_EN = 0 |
SAFETY_BUCK2_STAT1[3] SAFE state(4) NRES = 1, ENDRV/nIRQ = 0 |
YES |
| VBOOST | VSENSE3 | –5.0% to –2.5% | 2.5% to 5.0% | 6% to 10% | 21 µs to 39 µs | 21 µs to 39 µs | VMON_UV_STAT[3] RESET state if BOOST_UV_RST_EN = 1, No change in state if BOOST_UV_RST_EN = 0 NRES = 0, ENDRV/nIRQ = 0 if BOOST_UV_RST_EN = 1, No change in NRES or ENDRV/nIRQ if BOOST_UV_RST_EN = 0 |
VMON_OV_STAT[3] RESET state if BOOST_OV_RST_EN = 1, SAFE state if BOOST_OV_RST_EN = 0 NRES = 0, ENDRV/nIRQ = 0 if BOOST_OV_RST_EN = 1, NRES = 1, ENDRV/nIRQ = 0 if BOOST_OV_RST_EN = 0 |
SAFETY_BOOST_STAT1[3] SAFE state(5) NRES = 1, ENDRV/nIRQ = 0 |
YES |
| EXT_VSENSEx | EXT_VSENSEx | –4.8% to –3.0% | 3.0% to 4.8% | — | 21 µs to 39 µs | — | EXT_VMON_STAT[1:0] RESET state if EXT_VMONx_UV_RST_EN = 1, SAFE state if EXT_VMONx_UV_RST_EN = 0 AND EXT_VMONx_UV_IRQ_EN = 1 NRES = 0, ENDRV/nIRQ = 0 if EXT_VMONx_UV_RST_EN = 1, NRES = 1, ENDRV/nIRQ = 0 if EXT_VMONx_UV_RST_EN = 0 AND EXT_VMONx_UV_IRQ_EN = 1 |
EXT_VMON_STAT[5:4] RESET state if EXT_VMONx_OV_RST_EN = 1, SAFE state if EXT_VMONx_OV_RST_EN = 0 AND EXT_VMONx_OV_IRQ_EN = 1 NRES = 0, ENDRV/nIRQ = 0 if EXT_VMONx_OV_RST_EN = 1, NRES = 1, ENDRV/nIRQ = 0 if EXT_VMONx_OV_RST_EN = 0 AND EXT_VMONx_OV_IRQ_EN = 1 |
— | YES |
| VREG | VREG | 3.7 V to 3.9 V | 5.9 V to 6.5 V | — | UV: 24 µs to 40 µs OV: 10 µs to 20 µs | — | VMON_UV_STAT[4] OFF state NRES = 0, ENDRV/nIRQ = 0 |
VMON_OV_STAT[4] OFF state NRES = 0, ENDRV/nIRQ = 0 |
— | YES |
| VIO | VIO | — | 5.9 V to 6.5 V | — | 10 µs to 20 µs | — | — | VMON_OV_STAT[7] No change in state NRES and ENDRV/nIRQ HiZ as VIO gets disconnected(6) |
— | NO |