The ENDRV/nIRQ pin can be used in the system as an enable driver (ENDRV), independent safing enable or safety power-stage enable control signal, an external error interrupt (nIRQ) to the system MCU, or both. The device has no dedicated configuration bit to configure the mode (ENDRV mode or nIRQ mode) of the ENDRV/nIRQ pin. System-level requirements select how the ENDRV/nIRQ pin is used.

The default state of the ENDRV/nIRQ output driver is LOW. The state of the ENDRV/nIRQ pin can be activated in the DIAGNOSTIC and ACTIVE states. System-level diagnostics by the system MCU occur in the DIAGNOSTIC state, to confirm that the ENDRV/nIRQ output driver is controllable (as a system-level safety diagnostics requirement). In the ACTIVE state, the system MCU can use ENDRV to control (either activate or deactivate, or enable or disable) system-level peripherals or an nIRQ external interrupt to the system MCU. Activating the ENDRV/nIRQ driver (driving it high) requires system MCU activation (or MCU enable) by a SPI command, after the system's MCU services watchdog function to decrement watchdog failure counter to less than a programmed threshold value for ENDRV activation as defined by the WD_FC_ENDRV_TH[3:0] bits.

The ENDRV/nIRQ driver has a driver-error monitoring function that is enabled after the driver is activated (driven high). An error is detected each time the ENDRV/nIRQ pin is pulled low externally while the ENDRV/nIRQ pin output buffer is trying to drive it high.

During an active ABIST run when the device is in the DIAGNOSTIC or ACTIVE state, and if the ENDRV/nIRQ output driver is activated (driven high), the active ABIST comparator test toggles the activated ENDRV/nIRQ driver low for the duration of the ABIST run pulse test if any of the BUCKx/BOOST_OT_WARN_IRQ_EN bits are set. Driving the ENDRV/nIRQ driver low during the active ABIST test when the device is in the DIAGNOSTIC or ACTIVE state does not clear the ENDRV_EN control bit and the device does not change states.

When the activated ENDRV/nIRQ driver toggles from HIGH to LOW, the potential impact to the system could be one or a combination of the following:

• Disabled power stages
• Disabled safing switch (this switch is a redundant high-side switch for connecting the VBAT supply to the system-power stages.)
• Generated interrupt to the system MCU (when connected to the system MCU, the GPIO pin that is configured as an external interrupt source, edge, or level triggered.)

Figure 11-30 shows the driver and enable logic of the ENDRV/nIRQ pin.

1. When the condition is met, the device goes from the ACTIVE state to the SAFE state. No action occurs if the device is in the DIAGNOSTIC or SAFE state.
2. When the condition is met, the device stays in the ACTIVE state, if the MCU_ESM_RST_EN bit is set to 0b. When the condition is met, the device goes from the ACTIVE state to the RESET state, if the MCU_ESM_RST_EN bit is set to 1b. This transition occurs only if the MCU_ESM_FC_RST_TH[3:0] bit value is equal to or less than the MCU_ESM_FC_ENDRV_TH[3:0] bit value.
3. When the condition is met, the device does not go from the ACTIVE state to the SAFE state. No action occurs if the device is in the DIAGNOSTIC or SAFE state.
4. When the condition is met, the device goes from the ACTIVE state to the SAFE state.

Figure 11-30 ENDRV/nIRQ Driver and Logic