The integrated phase-locked loop (PLL) allows the device to synchronize the switched-mode regulator clocks to an external SYNC_IN input clock to help reduce EMI. When the TPS65313-Q1 device powers up, the device monitors the SYNC_IN pin for the presence of recurring clock edges. If the device detects activity on the SYNC_IN pin, the clock for the switched-mode regulators is derived from the external SYNC_IN clock. If the device does not detect any activity on the SYNC_IN pin, then the switched-mode regulators get a clock from the free-running VCO clock in the PLL.

When the system initially powers up without an external clock present at the SYNC_IN pin, the device enables the switched-mode regulators with the clock derived from the free-running VCO clock in the PLL. The device switches to an external clock source present at the SYNC_IN pin when the system powers up. The start of the regulator switching cycle is synchronized to the falling edge of the input clock at the SYNC_IN pin. If a loss-of-external clock event is detected, the clock source is switched to the free-running VCO clock to continue to regulate the output voltages.

An external clock should be connected to the SYNC_IN pin with a proper high-speed termination to avoid excessive ringing. The requirements on the external clock are as follows:

• A high-level voltage that is not lower than 2 V.
• A low-level voltage that is not higher than 0.4 V.
• A duty cycle that is from 10% to 90%.
• Both a positive and negative pulse width that are not shorter than 80 ns.

1. MODCLK: Internal spread spectrum modulated clock source for switching regulators.
2. SYSCLK: Internal system clock source.
3. DIG_SYSCLK_ERR / DIG_CLK_MON2 error / fault reaction by the device state machine is masked/disabled in device EEPROM and this has no impact to device overall functionality. However, if the fault is detected by this clock monitor, DIG_SYS_CLK_ERR and SYSCLK_ERR status bit will be still set and should be ignored.

Figure 11-4 Device Clock Tree and Monitors