10.1 Layout Guidelines

TI recommends the guidelines that follow for PCB layout of the TPS65320D-Q1 device.

• Inductor

Use a low-EMI inductor with a ferrite-type shielded core. Other types of inductors can also be used, however, these inductors must have low-EMI characteristics and be located away from the low-power traces and components in the circuit.

• Input Filter Capacitors

Locate input ceramic filter capacitors close to the VIN pin. TI recommends surface-mount capacitors to minimize lead length and reduce noise coupling.

• Feedback

Route the feedback trace for minimum interaction with any noise sources associated with the switching components. TI recommends to place the inductor away from the feedback trace to prevent creating an EMI noise source.

• Traces and Ground Plane

All power (high-current) traces must be as thick and short as possible. The inductor and output capacitors must be as close to each other as possible to reduce EMI radiated by the power traces because of high switching currents. In a two-sided PCB, TI recommends using ground planes on both sides of the PCB to help reduce noise and ground loop errors. The ground connection for the input capacitors, output capacitors, and device ground should connect to this ground plane, where the connection between input capacitors and the catch-diode is the most critical. In a multi-layer PCB, the ground plane separates the power plane (where high switching currents and components are) from the signal plane (where the feedback trace and components are) for improved performance. Also, arrange the components such that the switching-current loops curl in the same direction. Place the high-current components such that during conduction the current path is in the same direction. This placement prevents magnetic field reversal caused by the traces between the two half-cycles, and helps reduce radiated EMI.

10.2 Layout Example

Figure 24. TPS65320D-Q1 Layout Example