The TPS65400 offers the ability to output rails of higher currents by connecting SW1 and SW2 in parallel, or by connecting SW3 and SW4 in parallel. To configure this option, the COMP2 or COMP4 terminal must be tied to VDDA through a 1-kΩ resistor.

Upon the initialization sequence after a reset, the TPS65400 attempts to discharge the COMP terminal through a 2-kΩ internal resistor. When it detects that the COMP terminal is pulled high, it configures itself to operate in current sharing mode. If SW2 is set to current sharing mode, its PWM output is controlled by the error amplifier and COMP1 terminal of SW1 and set to the same frequency as SW1. Likewise, if SW4 is set to current sharing mode, its PWM output is controlled by the error amplifier and COMP3 terminal of SW3 and set to the same frequency as SW3. This means that the frequency settings for SW2 and SW4 in the EEPROM are ignored in that mode of operation.

When current sharing mode is detected on a particular pair, the output slave’s I²C access is invalid and the output slave’s default settings follow that of its master (see (00h) PAGE). The only exception is that the slave switcher PWM is a fixed 180° phase-shift from its master.