The RCLOCK_SYNC terminal can be used to synchronize the master clock switching frequency, F_OSC, with an external clock source or another TPS65400. The external clock signal (which can come from another TPS65400 CLK_OUT terminal) should be AC coupled to the RCLOCK_SYNC terminal as shown in Figure 8-10. Choose the ROSC value so that the fixed frequency is nominally 30% lower than the external synchronizing clock frequency. An internal protection diode clamps the low level of the synchronizing signal to approximately –0.5 V. The internal clock synchronizes to the rising edge of the external clock.

Figure 8-10 AC-Coupled Clock Synchronization

TI recommends to choose an AC-coupling capacitance in the range of 50 to 100 pF. Exceeding the recommended capacitance may inject excessive energy through the internal clamping diode structure present on the RCLOCK_SYNC terminal. The typical trip level of the synchronization terminal is 1.5 V. To ensure proper synchronization and to avoid damaging the IC, the peak-to-peak value (amplitude) should be between 2.5 V and V_DDA. The minimum duration of this pulse must be greater than 200 ns, and its maximum duration must be 200 ns less than the period of the switching cycle.

The external clock synchronization process begins after the TPS65400 is enabled and an external clock signal is detected. The frequency modulator adjusts the oscillator frequency to match the frequency of the pulses into the RCLOCK_SYNC terminal. It generally takes 50 cycles before the PWM frequency locks. If the external clock signal is removed after frequency synchronization, the master clock F_OSC drifts to the frequency selected by ROSC.