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ZHCSD04E November 2014 – March 2022 TPS65400

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

RGZ|48
- MPQF123F

散热焊盘机械数据 (封装 | 引脚)

RGZ|48
- QFND014T

订购信息

7.6 System Characteristics

The following specification table entries are specified by the design (component values provided in the typical application circuit are used). These parameters are not specified by production testing. minimum and max values apply over the full operating ambient temperature range (–40°C ≤ T_J ≤ 125°C), over the V_IN range = 5 to 12 V, and I_OUT range unless otherwise specified. L = 3.3 µH, DCR = 10.4 mΩ, V_OUT = 1.2 V, 1% FB resistor.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_LINEREG	Line regulation			0.1		%/V
V_LOADREG	Load regulation			0.1		%/A
t_r	VOUT step duration (t_r)	For 50-mV step		30		µs
t_s	VOUT step settling time (t_s)	For 50-mV step		30		µs
V_OVUV	VOUT step overshoot/undershoot	For 50-mV step		6		mV
	Efficiency (SW1 and SW2)	V_IN = 5 V, V_O = 1.2 V, I_OUT = 4 A, ƒ_sw = 500 kHz		77%
	Efficiency (SW1 and SW2)	V_IN = 12 V, V_O = 1.2 V, I_OUT = 4 A, ƒ_sw = 500 kHz		76%
	Efficiency (SW3 and SW4)	V_IN = 5 V, V_O = 1.2 V, I_OUT = 2 A, ƒ_sw= 500 kHz		77%
	Efficiency (SW3 and SW4)	V_IN = 12 V, V_O = 1.2 V, I_OUT = 2 A, ƒ_sw= 500 kHz		74%
IOUT_match	Average (⁽¹⁾) current sharing accuracy (SW1 and SW2, SW3 and SW4)	I_load = I_OUTmax		20%
IPK_match	Peak current (⁽²⁾) sharing accuracy (SW1 and SW2, SW3 and SW4)	I_load = I_OUTmax			20%
t_acc	Timing accuracy for delays and restarts		–10%		10%
t_{reset_delay}	Time after RSTn or CE is released for power sequence to begin	Default value		1		ms
t_{reset_delay_max0}	Minimum delay after reset is released for power sequence to begin	t_{reset_delay} set to 0 ms			1.1	ms

(1) Average current sharing accuracy is highly dependent on the matching of the inductor and capacitor.

(2) Peak current sharing accuracy refers to the max inductor current in each phase.