Layout is a critical portion of high-current multi-channel DC-DC. Follow these guidelines for layout. See Section 11.2 for a PCB layout example.

• Place VOUT and SW on the top layer and an inner power plane for VIN.
• Also on the top layer, fit connections for the remaining pins of TPS65400 and a large top-side area filled with ground.
• Connect the top layer ground area to the internal ground layer or layers using vias at the input bypass capacitor, the output filter capacitor, and directly under the TPS65400 device to provide a thermal path from the power pad to ground.
• Tie the AGND pin directly to the power pad under the IC.
• For operation at full-rated load, the top-side ground area together with the internal ground plane must provide adequate heat dissipating area.
• Several signals paths conduct fast-changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies' performance. To help eliminate these problems, bypass the VIN pin to ground with a low-ESR ceramic bypass capacitor with X5R or X7R dielectric. Take care to minimize the loop area formed by the bypass capacitor connections, the VIN pins, and the ground connections. Because the SW connection is the switching node, the output inductor should be located close to the SW pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling.
• The output filter capacitor ground should use the same power ground trace as the VIND input bypass capacitor. Try to minimize this conductor length while maintaining adequate width.
• The compensation should be as close as possible to the COMP pins. The COMP and ROSC pins are sensitive to noise so the components associated to these pins should be located as close as possible to the IC and routed with minimal lengths of trace.
• The VFB node is a high-impedance analog node which is easier to pick noise on board. Keep FB node trace as short as possible.