Figure 9-2 shows an internal sequencing schematic example where only switchers 1 to 3 are used for a set of timing requirements. If the internal configuration and fault handling is sufficient, and provided that the user configures the chip through SDA/SCL before placing it on a target board, then it is not necessary for a supervisory and housekeeping host controller chip like a MCU or DSP to be connected to the TPS65400. In such a case, digital terminals PGOOD, SSx/ PG, SDA/SCL, I2CALERT, and CLK_OUT can be left unconnected with no pull-ups required, during normal operation. RST_N can be tied directly to VDDD (no pull-up required). I2CADDR can be tied directly to VDDD after programming. Control line CE can be left unconnected if the chip is constantly powered after VIN is provided.

PGOOD dependence disabled, switcher 4 disabled

Figure 9-2 Example Timing Diagram for Internal Sequencing