The master clock frequency, F_OSC, can be set by external resistor on the RCLOCK_SYNC terminal, or by synchronizing with an external clock. To set using an external resistor, use this formula.

Figure 8-8 Frequency vs R_osc

To sync to an external source, an AC-coupled signal should be applied to the terminal. A fixed resistor should still be connected to set a minimum frequency. The frequency of the input signal to synchronize with should always be higher than the minimum frequency. If the internal PLL cannot synchronize, the switchers will fall back to the minimum frequency set by the resistor. The CLK_OUT terminal outputs the master clock F_OSC.

The PWM frequency of each switcher is determined by this master clock frequency and an I²C-programmable choice of 4 divider ratios (1, 2, 4, or 8) by setting CLK_DIV (see (D7h) FREQUENCY_PHASE).

A. The frequency modulator is used for external clock synchronization.

Figure 8-9 Diagram of PWM Clock Generation

The intent of the individual divider ratios is to allow users to set the frequency of each switcher independently. For example, with a master clock F_OSC of 1.1 MHz, SW1 and SW2 have a divider ratio of 4 for a 275-kHz PWM, and SW3 and SW4 have a divider ratio of 1 for a PWM frequency of 1.1 MHz. Select the divider ratio so that the PWM frequency stays within the range of 275 kHz to 2.2 MHz for whichever master clock frequency is set.

In addition to selecting the frequency, each switcher can have its PWM frequency delayed. This enables the designer to minimize ripple current by properly selecting the delays so that the switching frequencies are out of phase. The default switching frequency is at CLK_DIV = F_OSC / 1 with PHASE_DELAY for SW1 at 0°, SW2 at 180°, SW3 at 90°, and SW4 at 270°. More information on frequency selection and delay is given in (D7h) FREQUENCY_PHASE.