5.3.2.1.1 Sync Clock Functionality

The TPS659037 device contains a SYNCDCDC input to sync DC-DCs with the external clock.

In forced PWM mode, SMPSs are synchronized on an external input clock (SYNCDCDC) whereas in Eco-mode or if the SYNCDCDC pin is grounded, the switching frequency is based on an internal RC oscillator. The clock generated from the internal RC oscillator can be output through GPIO5 to provide synchronization clock to external SMPSs. For PWM mode, a PLL is present to buffer the external input clock to create nine clock signals for the nine SMPSs with different phases.

The sync clock dither specification parameters are based on a triangular dither pattern, but other patterns that comply with the minimum and maximum sync frequency range and the maximum dither slope can also be used.

Figure 5-1 Sync Clock Range and Dither

The ollowing figure shows ƒ_(SYNC), the frequency of SYNCDCDC input clock and ƒ_SW, the frequency of PLL output signal.

When there is no clock present on SYNCDCDC pin, the PLL generates a clock with a frequency equal to ƒ_(FALLBACK).

If a clock is present on SYNCDCDC pin with a frequency between ƒ_{(SAT_LO)} and ƒ_{(SAT_HI)}, then the PLL is synchronised on SYNCDCDC clock and generates a clock with frequency equal to ƒ_(SYNC).

If ƒ_(SYNC) is higher than ƒ_{(SAT_HI)}, then the PLL generates a clock with a frequency equal to ƒ_{(SAT_HI)}.

If ƒ_(SYNC) is smaller than ƒ_{(SAT_LO)}, then the PLL generates a clock with a frequency equal to ƒ_{(SAT_LO)}.

Figure 5-2 Sync Clock Saturation and Frequency Fallback