ZHCSEF7G December   2014  – February 2019 TPS659037

PRODUCTION DATA.  

  1. 1 器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 简化方框图
  2. 2 修订历史记录
  3. 3 Pin Configuration and Functions
    1.     Pin Functions
  4. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics: Latch Up Rating
    6. 4.6  Electrical Characteristics: LDO Regulator
    7. 4.7  Electrical Characteristics: Dual-Phase (SMPS12 and SMPS45) and Triple-Phase (SMPS123 and SMPS457) Regulators
    8. 4.8  Electrical Characteristics: Stand-Alone Regulators (SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9)
    9. 4.9  Electrical Characteristics: Reference Generator (Bandgap)
    10. 4.10 Electrical Characteristics: 16-MHz Crystal Oscillator, 32-kHz RC Oscillator, and Output Buffers
    11. 4.11 Electrical Characteristics: DC-DC Clock Sync
    12. 4.12 Electrical Characteristics: 12-Bit Sigma-Delta ADC
    13. 4.13 Electrical Characteristics: Thermal Monitoring and Shutdown
    14. 4.14 Electrical Characteristics: System Control Threshold
    15. 4.15 Electrical Characteristics: Current Consumption
    16. 4.16 Electrical Characteristics: Digital Input Signal Parameters
    17. 4.17 Electrical Characteristics: Digital Output Signal Parameters
    18. 4.18 Electrical Characteristics: I/O Pullup and Pulldown
    19. 4.19 I2C Interface Timing Requirements
    20. 4.20 SPI Timing Requirements
    21. 4.21 Typical Characteristics
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1  Power Management
      2. 5.3.2  Power Resources (Step-Down and Step-Up SMPS Regulators, LDOs)
        1. 5.3.2.1 Step-Down Regulators
          1. 5.3.2.1.1 Sync Clock Functionality
          2. 5.3.2.1.2 Output Voltage and Mode Selection
          3. 5.3.2.1.3 Current Monitoring and Short Circuit Detection
          4. 5.3.2.1.4 POWERGOOD
          5. 5.3.2.1.5 DVS-Capable Regulators
          6. 5.3.2.1.6 Non DVS-Capable Regulators
          7. 5.3.2.1.7 Step-Down Converters SMPS12 and SMPS123
            1.         a. Dual-Phase SMPS and Stand-Alone SMPS
            2.         b. Triple Phase SMPS
          8. 5.3.2.1.8 Step-Down Converter SMPS45 and SMPS457
          9. 5.3.2.1.9 Step-Down Converters SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9
        2. 5.3.2.2 LDOs – Low Dropout Regulators
          1. 5.3.2.2.1 LDOVANA
          2. 5.3.2.2.2 LDOVRTC
          3. 5.3.2.2.3 LDO Bypass (LDO9)
          4. 5.3.2.2.4 LDOUSB
          5. 5.3.2.2.5 Other LDOs
      3. 5.3.3  Long-Press Key Detection
      4. 5.3.4  RTC
        1. 5.3.4.1 General Description
        2. 5.3.4.2 Time Calendar Registers
          1. 5.3.4.2.1 TC Registers Read Access
          2. 5.3.4.2.2 TC Registers Write Access
        3. 5.3.4.3 RTC Alarm
        4. 5.3.4.4 RTC Interrupts
        5. 5.3.4.5 RTC 32-kHz Oscillator Drift Compensation
      5. 5.3.5  GPADC – 12-Bit Sigma-Delta ADC
        1. 5.3.5.1 Asynchronous Conversion Request (SW)
        2. 5.3.5.2 Periodic Conversion Request (AUTO)
        3. 5.3.5.3 Calibration
      6. 5.3.6  General-Purpose I/Os (GPIO Pins)
        1. 5.3.6.1 REGEN Output
      7. 5.3.7  Thermal Monitoring
        1. 5.3.7.1 Hot-Die Function (HD)
        2. 5.3.7.2 Thermal Shutdown (TS)
        3. 5.3.7.3 Temperature Monitoring With External NTC Resistor or Diode
      8. 5.3.8  Interrupts
      9. 5.3.9  Control Interfaces
        1. 5.3.9.1 I2C Interfaces
          1. 5.3.9.1.1 I2C Implementation
          2. 5.3.9.1.2 F/S Mode Protocol
          3. 5.3.9.1.3 HS Mode Protocol
        2. 5.3.9.2 Serial-Peripheral Interface (SPI)
          1. 5.3.9.2.1 SPI Modes
          2. 5.3.9.2.2 SPI Protocol
      10. 5.3.10 Device Identification
    4. 5.4 Device Functional Modes
      1. 5.4.1  Embedded Power Controller
      2. 5.4.2  State Transition Requests
        1. 5.4.2.1 ON Requests
        2. 5.4.2.2 OFF Requests
        3. 5.4.2.3 SLEEP and WAKE Requests
      3. 5.4.3  Power Sequences
      4. 5.4.4  Startup Timing and RESET_OUT Generation
      5. 5.4.5  Power On Acknowledge
        1. 5.4.5.1 POWERHOLD Mode
        2. 5.4.5.2 AUTODEVON Mode
      6. 5.4.6  BOOT Configuration
        1. 5.4.6.1 Boot Pin Selection
      7. 5.4.7  Reset Levels
      8. 5.4.8  Warm Reset
      9. 5.4.9  RESET_IN
      10. 5.4.10 Watchdog Timer (WDT)
      11. 5.4.11 System Voltage Monitoring
        1. 5.4.11.1 Generating a POR
  6. 6 Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1  Recommended External Components
        2. 6.2.2.2  SMPS Input Capacitors
        3. 6.2.2.3  SMPS Output Capacitors
        4. 6.2.2.4  SMPS Inductors
        5. 6.2.2.5  LDO Input Capacitors
        6. 6.2.2.6  LDO Output Capacitors
        7. 6.2.2.7  VCC1
          1. 6.2.2.7.1 Meeting the Power Down Sequence
          2. 6.2.2.7.2 Maintaining Sufficient Input Voltage
        8. 6.2.2.8  VIO_IN
        9. 6.2.2.9  16-MHz Crystal
        10. 6.2.2.10 GPADC
      3. 6.2.3 Application Curves
  7. 7 Power Supply Recommendations
  8. 8 Layout
    1. 8.1 Layout Guidelines
    2. 8.2 Layout Example
  9. 9 器件和文档支持
    1. 9.1 器件支持
      1. 9.1.1 第三方米6体育平台手机版_好二三四免责声明
    2. 9.2 文档支持
      1. 9.2.1 相关文档
    3. 9.3 接收文档更新通知
    4. 9.4 社区资源
    5. 9.5 商标
    6. 9.6 静电放电警告
    7. 9.7 Glossary
  10. 10机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

2 修订历史记录

Changes from F Revision (January 2018) to G Revision

  • Updated the LDOVRTC_OUT pulldown resistor recommendation to only include applicable silicon revisions. Go
  • Changed ESD Ratings for charge device model on 6 pins Go
  • Clarified that LDO1 and LDO2 input pins are not included in this minimum recommended operating voltage. See Electrical Characteristics: LDO Regulators for more information. Go
  • Changed minimum recommended operating condition of OSC16MIN from 0V to -0.7V Go
  • Added LDO and SMPS output capacitance footnote Go
  • Changed VSYS_LO hysteresis from 95mV to 75mV Go
  • Updated Caution statement to only include applicable silicon revisions. Go
  • Changed discharge resistance to match electrical characteristics table Go
  • Added information about shutdown timing during short circuit detection Go
  • Updated POWERGOOD description to clarify multi-phase operation. Go
  • Updated LDOVRTC note to only include applicable silicon revisions. Go
  • Added details on identifying device version. Go
  • Added typical debounce time from POWERHOLD to the enable of the first rail in the power sequence. Go
  • Added VSYS_LO note for applicable silicon revisions. Go
  • Updated POR requirements to only include applicable silicon revisions. Go
  • SMPS and LDO output capacitance specification further explained Go
  • Added design considerations for VCC1 capacitance to support loss of powerGo
  • Corrected 9-Vpp with 7V absolute maximum specification in the Layout Guidelines sectionGo
  • Updated requirements relating to measurement of high-side and low-side FETs in the Layout Guidelines sectionGo
  • Updated images and description on differential measurements across high-side and low-side FETs Go

Changes from E Revision (July 2017) to F Revision

  • Deleted pullup and pulldown from BOOT0 pin description Go
  • Deleted the voltage mode to the I/O digital supply voltage, VIO_IN parameter from the Recommended Operating Conditions tableGo
  • Added 2-A mode for SMPS6 in the test conditions for high-side and low-side MOSFET forward current limit and low-side MOSFET negative current limit in the Electrical Characteristics: Stand-Alone Regulators (SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9) tableGo
  • Added the number of active SMPS phases (K) to the equation for the temperature compensated result in the Current Monitoring and Short Circuit Detection sectionGo
  • Added additional description of SMPS short detection and recovery behavior Go
  • Added equation to convert GPADC code to internal die temperatureGo
  • Added description of VIO power-up timing, and updated start up timing diagramGo
  • Added additional description of VSYS_LO functionalityGo
  • Changed 静电放电注意事项 声明Go

Changes from D Revision (April 2016) to E Revision

  • Deleted CLK32KGO from the Startup Timing DiagramGo
  • Added OTP note to the Application SchematicGo
  • Changed the VIO_GND connection to C6 in the Typical Application SchematicGo
  • Updated part numbers and settings for released devices in the Design Parameters table Go
  • Added 接收文档更新通知 部分Go

Changes from C Revision (November 2015) to D Revision

  • Changed the LDOVRTC_OUT pin description in the Pin Functions table Go
  • Changed the typical value for the channel 11 SMPS output current measurement gain factor parameter in the 12-Bit Sigma-Delta ADC Characteristics tableGo
  • Changed the typical value for the channel 11 SMPS output current measurement current offset parameter in the 12-Bit Sigma-Delta ADC Characteristics tableGo
  • Added maximum current of LDOVRTC in BACKUP and OFF statesGo
  • Added a note to the LDOVRTC section Go
  • Added additional description of POR in System Voltage Monitoring sectionGo
  • Updated part numbers and settings for released devices in the Design Parameters table Go

Changes from B Revision (November 2015) to C Revision

  • Added statement to the Current Monitoring and Short Circuit Detection section that the SMPS_SHORT_REGISTER bit will keep a resource off until it is clearedGo

Changes from A Revision (September 2015) to B Revision

  • Changed 将器件状态从预告信息 更改成了量产数据Go

Changes from * Revision (December 2014) to A Revision

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