5.3.9.2.1 SPI Modes

The SPI does not have access to the OTP and DVS registers (slave device address 0x4B & 0x12) of the device. The SPI_PAGE_CTRL.SPI_PAGE_ACCESS regsiter can be configured to access all other registers (slave device address 0x48, 0x49, & 0x4A) by:

• SPI_PAGE_CTRL.SPI_PAGE_ACCESS = 0: Page1 = 0x48, Page2 = 0x49
• SPI_PAGE_CTRL.SPI_PAGE_ACCESS = 1: Page1 = 0x48, Page3 = 0x4A

This SPI supports two access modes (Note: all shifts are done MSB first (Data, Address, Page):

• Single access (read or write)
  • This consists of fetching and storing one single data location. The protocol is depicted in Figure 5-15.
  • The R/W bit is always provided first, followed by page address and register address fields. When R/W = 0, a read access is performed. When R/W = 1, a write access is performed.
  • 1 burst bit indicates if following transfer is a single access (BURST = 0) or a burst access (BURST = 1).
  • 4 unused bits follow the burst bit and finally the 8-bit data is either shifted in (write) or out (read).
  • For a write access, the data output line SDO is invalid (useless) during the whole transaction.
  • For a read access, the data output line SDO is invalid during the unused bits (time slot used for data fetch) and then becomes active or valid after the unused bits.
• Burst access (read or write)
  • This consists of fetching and storing several data at contiguous locations. The protocol is depicted in Figure 5-16.
  • The R/W bit is always provided first, followed by page address and register address fields. When R/W = 0, a read access is performed. When R/W = 1, a write access is performed.
  • 1 burst bit indicates if following transfer is a single access (BURST = 0) or a burst access (BURST = 1).
  • 4 unused bits follow the burst bit and finally packets of 8-bit data are either shifted in (write) or out (read).
  • The transaction remains active as long as the SCE signal is maintained high by the host.
  • The address is automatically incremented internally for each new 8-bit packet received.
  • The host must pull the SCE signal low after a complete 8-bit data is transferred, otherwise the last transaction is discarded.
  • For a write access, the data output line SDO is invalid (useless) during the whole transaction.
  • For a read access, the data output line SDO is invalid during the unused bits (time slot used for data fetch) and then becomes active or valid after the unused bits.