ZHCSG94L August 2013 – February 2019 TPS659038-Q1 , TPS659039-Q1
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
PWRON, RPWRON | ||||||
VIL | Low-level input voltage related to VSYS (VCC1 pin reference) | –0.3 | 0 | 0.35 × VSYS | V | |
VIH | High-level input voltage related to VSYS (VCC1 pin reference) | 0.65 × VSYS | VSYS | VSYS + 0.3 ≤ 5.25 | V | |
Hysteresis | 0.05 × VSYS | V | ||||
ENABLE1, GPIO_4, GPIO_6, I2C1_SCL_SCK, I2C1_SDA_SDI, I2C2_SCL_SCE, I2C2_SDA_SDO | ||||||
VIL | Low-level input voltage related to VIO (VIO_IN pin reference) | –0.3 | 0 | 0.3 × VIO | V | |
VIH | High-level input voltage related to VIO (VIO_IN pin reference) | 0.7 × VIO | VIO | VIO + 0.3 | V | |
Hysteresis | 0.05 × VIO | V | ||||
CB | Capacitive load for SDA and SCL in I2C mode | 400 | pF | |||
BOOT0, PWRDOWN, RESET_IN, NSLEEP, NRESWARM, GPIO_0, GPIO_1, GPIO_2, GPIO_3, GPIO_5, GPIO_7 OR POWERHOLD | ||||||
VIL | Low-level input voltage related to VRTC | –0.3 | 0 | 0.3 × VRTC | V | |
VIH | High-level input voltage related to VRTC | 0.7 × VRTC | VRTC | VRTC + 0.3 | V | |
Hysteresis | 0.05 × VRTC | V | ||||
Input voltage maximum for RESET_IN and GPIO_7 | 5.25 | V | ||||
BOOT1 | ||||||
VIL | Low-level input voltage related to VRTC | –0.3 | 0 | 0.3 × VRTC | V | |
VIH | High-level input voltage related to VRTC | 0.95 × VRTC | VRTC | VRTC + 0.3 | V |