6.3.8 Interrupts

Table 6-6 lists the TPS65903x-Q1 interrupts.

These interrupts are split into four register groups (INT1, INT2, INT3, INT4) and each group has three associated control registers:

• INTx_STATUS: Reflects which interrupt source has triggered an interrupt event
• INTx_MASK: Used to mask any source of interrupt, to avoid generating an interrupt on a specified source
• INTx_LINE_STATE: Reflects the real-time state of each line associated to each source of interrupt

The INT4 register group has two additional registers, INT4_EDGE_DETECT1 and
INT4_EDGE_DETECT2, to independently configure rising and falling edge detection.

All interrupts are logically combined on a single output line INT (default active low). This line is used as an external interrupt line to warn the host processor of any interrupt event that has occurred within the device. The host processor has to read the interrupt status registers (INTx_STATUS) through the control interface (I²C or SPI) to identify the interrupt source(s). Any interrupt source can be masked by programming the corresponding mask register (INTx_MASK). When an interrupt is masked, its associated event detection mechanism is disabled. Therefore the corresponding STATUS bit is not updated and the INT line is not triggered if the masked event occurs. Any event happening while its corresponding interrupt is masked is lost. If an interrupt is masked after it has been triggered (event has occurred and has not yet been cleared), then the STATUS bit reflects the event until it is cleared and it does not trigger again if a new event occurs (because it is now masked).

Because some interrupts are sources of ON requests (see Table 6-6), source masking can be used to mask a specific device switch-on event. Because an active interrupt line INT is treated as an ON request, any interrupt not masked must be cleared to allow the execution of a SLEEP sequence of the device when requested.

The INT line polarity and interrupts clearing method can be configured using the INT_CTRL register.

An INT line event can be provided to the host in either SLEEP or ACTIVE mode, depending on the setting of the OSC_THERM_CTRL.INT_MASK_IN_SLEEP bit.

When a new interrupt occurs while the interrupt line INT is still active (not all interrupts have been cleared), then:

• If the new interrupt source is the same as the one that has already triggered the INT line, it can be discarded or stored as a pending interrupt depending on the setting of the INT_CTRL.INT_PENDING bit.
  • When the INT_CTRL.INT_PENDING bit is active (default), then any new interrupt event occurring on the same source (while the INT line is still active) is stored as a pending interrupt. Because only one level of pending interrupt can be stored for a given source, when several events (more than two) occur on the same source, only the last one is stored. While an interrupt is pending, two accesses are needed (either read or write) to clear the STATUS bit: one access for the actual interrupt and another for the pending interrupt. Note: two consecutive read or write operations to the same register clear only one interrupt. Another register must be accessed between the two read or write clear operations. Example for clear-on-read: when INT signal is active, read all four INTx_STATUS registers in sequence to collect status of all potential interrupt sources. Read access clears the full register for an active or actual interrupt. If the INT line is still active, repeat read sequence to check and clear pending interrupts.
  • When the INT_CTRL.INT_PENDING bit is inactive, then any new interrupt event occurring on the same source (while the INT line is still active) is discarded. Note: two consecutive read or write operations to the same register clear only one interrupt. Another register must be accessed between the two read or write clear operations.
• If the new interrupt source is different from the one that already triggered the INT line, then it is stored immediately into its corresponding STATUS bit.

To clear the interrupt line, all status registers must be cleared. The clearing of all status registers is achieved by using a clear-on-read or a clear-on-write method. The clearing method is selectable though the INT_CTRL.INT_CLEAR bit. Once set, the clearing method applies to all bits for all interrupts.

• Clear-on-read
  • Read access to a single status register clears all the bits for only this specific register (8 bits). Therefore, clearing all interrupts requests to read the four status registers. If the INT line is still active when the four read accesses complete, then another interrupt event has occurred during the read process; therefore the read sequence must be repeated.
• Clear-on-write
  • This method is bit-based; setting a specific bit to 1 clears only the written bit. Therefore, to clear a complete status register, 0xFF must be written. Clearing all interrupts requests to write 0xFF into the four status registers. If the INT line is still active when the four write accesses are complete, then another interrupt event has occurred during the write process; therefore the write sequence must be repeated.