SWCS071C August   2012  – August 2017

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Default Settings
  4. 4 Pin Configuration and Functions
    1. 4.1 Pin Functions
  5. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Characteristics
    5. 5.5  Electrical Characteristics - DCDC1, DCDC2, and DCDC3
    6. 5.6  Electrical Characteristics - DCDC4
    7. 5.7  Electrical Characteristics - LDOs
    8. 5.8  Electrical Characteristics - Digital Inputs, Digital Outputs
    9. 5.9  Electrical Characteristics - VMON Voltage Monitor, VDDIO, Undervoltage Lockout (UVLO), and LDOAO
    10. 5.10 Electrical Characteristics - Load Switch
    11. 5.11 Electrical Characteristics - LED Drivers
    12. 5.12 Electrical Characteristics - Thermal Monitoring and Shutdown
    13. 5.13 Electrical Characteristics - 32-kHz RC Clock
    14. 5.14 SPI Interface Timing Requirements
    15. 5.15 I2C Interface Timing Requirements
    16. 5.16 Typical Characteristics
  6. 6 Parameter Measurement Information
    1. 6.1 I2C Timing Diagrams
    2. 6.2 SPI Timing Diagram
  7. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Linear Regulators
      1. 7.3.1 Low Quiescent Current Mode (Eco-mode™)
      2. 7.3.2 Output Discharge
      3. 7.3.3 Thermal Shutdown
      4. 7.3.4 LDO Enable
      5. 7.3.5 LDO Voltage Range
      6. 7.3.6 LDO Power Good Comparator
    4. 7.4  Step-Down Converters
      1. 7.4.1 PWM/PFM Mode
      2. 7.4.2 Low Quiescent Current Mode
      3. 7.4.3 Output Voltage Monitoring
      4. 7.4.4 Output Discharge
      5. 7.4.5 Thermal Shutdown
      6. 7.4.6 Step-Down Converter ENABLE
      7. 7.4.7 Step-Down converter SOFT START
    5. 7.5  GPIOs
    6. 7.6  Power State Machine
    7. 7.7  Transition Conditions
    8. 7.8  Implementation of Internal Power-Up and Power-Down Sequencing
    9. 7.9  EN1, EN2, EN3, EN4, Resources Control
    10. 7.10 SLEEP State Control
    11. 7.11 Registers SET_OFF, KEEP_ON and DEF_VOLT Used in SLEEP State; CONFIG2 = 1
    12. 7.12 Registers SET_OFF, KEEP_ON and DEF_VOLT Used for Resources Assigned to an External Enable Pin; CONFIG2 = 1
    13. 7.13 Registers SET_OFF, KEEP_ON and DEF_VOLT for Resources Assigned to Pins PWR_REQ, CLK_REQ1 and CLK_REQ2; CONFIG2 = 0
    14. 7.14 Voltage Scaling Interface Control Using _OP and _AVS Registers with I2C or SPI Interface
    15. 7.15 Voltage Scaling Using the VCON Decoder on Pins VCON_PWM and VCON_CLK
    16. 7.16 Configuration Pins CONFIG1, CONFIG2 and DEF_SPI_I2C-GPIO
    17. 7.17 VDDIO Voltage for Push-Pull Output Stages
    18. 7.18 Digital Signal Summary
    19. 7.19 TPS659121 On/Off Operation With E450, E500
      1. 7.19.1 TPS659121 Power Up From Battery or 5-V USB Supply; CONFIG1=LOW
      2. 7.19.2 TPS659121 Power Up From 3.3-V Host Supply; CONFIG1=LOW
    20. 7.20 TPS659122 On/Off Operation for CONFIG1=HIGH
      1. 7.20.1 TPS659122 Power Up With CONFIG1=HIGH
      2. 7.20.2 TPS659121, TPS659122 Power-Off Sequence With CONFIG1=HIGH
    21. 7.21 TPS659122 On/Off Operation for CONFIG1=LOW
      1. 7.21.1 TPS659122 Power Up With CONFIG1=LOW
      2. 7.21.2 TPS659122 Power-Off Sequence With CONFIG1=LOW
    22. 7.22 Interfaces
    23. 7.23 Serial Peripheral Interface
    24. 7.24 I2C Interface
      1. 7.24.1 I2C Implementation
      2. 7.24.2 F/S-Mode Protocol
      3. 7.24.3 H/S-Mode Protocol
    25. 7.25 Thermal Monitoring and Shutdown
    26. 7.26 Load Switch
    27. 7.27 LED Driver
    28. 7.28 Memory
      1. 7.28.1 Register Format
      2. 7.28.2 Register Descriptions
        1. 7.28.2.1 DCDC Registers
          1. 7.28.2.1.1  DCDC1_CTRL (00h)
          2. 7.28.2.1.2  DCDC2_CTRL (01h)
          3. 7.28.2.1.3  DCDC3_CTRL (02h)
          4. 7.28.2.1.4  DCDC4_CTRL (03h)
          5. 7.28.2.1.5  DCDC1_OP (04h)
          6. 7.28.2.1.6  DCDC1_AVS (05h)
          7. 7.28.2.1.7  DCDC1_LIMIT (06h)
          8. 7.28.2.1.8  DCDC2_OP (07h)
          9. 7.28.2.1.9  DCDC2_AVS (08h)
          10. 7.28.2.1.10 DCDC2_LIMIT (09h)
          11. 7.28.2.1.11 DCDC3_OP (0Ah)
          12. 7.28.2.1.12 DCDC3_AVS (0Bh)
          13. 7.28.2.1.13 DCDC3_LIMIT (0Ch)
          14. 7.28.2.1.14 DCDC4_OP (0Dh)
          15. 7.28.2.1.15 DCDC4_AVS (0Eh)
          16. 7.28.2.1.16 DCDC4_LIMIT (0Fh)
          17. 7.28.2.1.17 VDCDCx Range Settings
          18. 7.28.2.1.18 DCDCx Voltage Settings
        2. 7.28.2.2 LDO Registers
          1. 7.28.2.2.1  LDO1_OP (10h)
          2. 7.28.2.2.2  LDO1_AVS (11h)
          3. 7.28.2.2.3  LDO1_LIMIT (12h)
          4. 7.28.2.2.4  LDO2_OP (13h)
          5. 7.28.2.2.5  LDO2_AVS (14h)
          6. 7.28.2.2.6  LDO2_LIMIT (15h)
          7. 7.28.2.2.7  LDO3_OP (16h)
          8. 7.28.2.2.8  LDO3_AVS (17h)
          9. 7.28.2.2.9  LDO3_LIMIT (18h)
          10. 7.28.2.2.10 LDO4_OP (19h)
          11. 7.28.2.2.11 LDO4_AVS (1Ah)
          12. 7.28.2.2.12 LDO4_LIMIT (1Bh)
          13. 7.28.2.2.13 LDO5 (1Ch)
          14. 7.28.2.2.14 LDO6 (1Dh)
          15. 7.28.2.2.15 LDO7 (1Eh)
          16. 7.28.2.2.16 LDO8 (1Fh)
          17. 7.28.2.2.17 LDO9 (20h)
          18. 7.28.2.2.18 LDO10 (21h)
        3. 7.28.2.3 LDO Voltage Settings
        4. 7.28.2.4 DEVCTRL Registers
          1. 7.28.2.4.1  THRM_REG (22h)
          2. 7.28.2.4.2  CLK32KOUT (23h)
          3. 7.28.2.4.3  DEVCTRL (24h)
          4. 7.28.2.4.4  DEVCTRL2 (25h)
          5. 7.28.2.4.5  I2C_SPI_CFG (26h)
          6. 7.28.2.4.6  KEEP_ON1 (27h)
          7. 7.28.2.4.7  KEEP_ON2 (28h)
          8. 7.28.2.4.8  SET_OFF1 (29h)
          9. 7.28.2.4.9  SET_OFF2 (2Ah)
          10. 7.28.2.4.10 DEF_VOLT (2Bh)
          11. 7.28.2.4.11 LDO Sleep Mode Behavior
          12. 7.28.2.4.12 DEF_VOLT_MAPPING (2Ch)
          13. 7.28.2.4.13 DISCHARGE1 (2Dh)
          14. 7.28.2.4.14 DISCHARGE2 (2Eh)
          15. 7.28.2.4.15 EN1_SET1 (2Fh)
          16. 7.28.2.4.16 EN1_SET2 (30h)
          17. 7.28.2.4.17 EN2_SET1 (31h)
          18. 7.28.2.4.18 EN2_SET2 (32h)
          19. 7.28.2.4.19 EN3_SET1 (33h)
          20. 7.28.2.4.20 EN3_SET2 (34h)
          21. 7.28.2.4.21 EN4_SET1 (35h)
          22. 7.28.2.4.22 EN4_SET2 (36h)
          23. 7.28.2.4.23 PGOOD (37h)
          24. 7.28.2.4.24 PGOOD2 (38h)
          25. 7.28.2.4.25 INT_STS (39h)
          26. 7.28.2.4.26 INT_MSK (3Ah)
          27. 7.28.2.4.27 INT_STS2 (3Bh)
          28. 7.28.2.4.28 INT_MSK2 (3Ch)
          29. 7.28.2.4.29 INT_STS3 (3Dh)
          30. 7.28.2.4.30 INT_MSK3 (3Eh)
          31. 7.28.2.4.31 INT_STS4 (3Fh)
          32. 7.28.2.4.32 INT_MSK4 (40h)
          33. 7.28.2.4.33 GPIO1 (41h)
          34. 7.28.2.4.34 GPIO2 (42h)
          35. 7.28.2.4.35 GPIO3 (43h)
          36. 7.28.2.4.36 GPIO4 (44h)
          37. 7.28.2.4.37 GPIO5 (45h)
          38. 7.28.2.4.38 VMON (46h)
          39. 7.28.2.4.39 LEDA_CTRL1 (47h)
          40. 7.28.2.4.40 LEDA_CTRL2 (48h)
          41. 7.28.2.4.41 LEDA_CTRL3 (49h)
          42. 7.28.2.4.42 LEDA_CTRL4 (4Ah)
          43. 7.28.2.4.43 LEDA_CTRL5 (4Bh)
          44. 7.28.2.4.44 LEDA_CTRL6 (4Ch)
          45. 7.28.2.4.45 LEDA_CTRL7 (4Dh)
          46. 7.28.2.4.46 LEDA_CTRL8 (4Eh)
          47. 7.28.2.4.47 LEDB_CTRL1 (4Fh)
          48. 7.28.2.4.48 LEDB_CTRL2 (50h)
          49. 7.28.2.4.49 LEDB_CTRL3 (51h)
          50. 7.28.2.4.50 LEDB_CTRL4 (52h)
          51. 7.28.2.4.51 LEDB_CTRL5 (53h)
          52. 7.28.2.4.52 LEDB_CTRL6 (54h)
          53. 7.28.2.4.53 LEDB_CTRL7 (55h)
          54. 7.28.2.4.54 LEDB_CTRL8 (56h)
          55. 7.28.2.4.55 LEDC_CTRL1 (57h)
          56. 7.28.2.4.56 LEDC_CTRL2 (58h)
          57. 7.28.2.4.57 LEDC_CTRL3 (59h)
          58. 7.28.2.4.58 LED_CTRL4 (5Ah)
          59. 7.28.2.4.59 LEDC_CTRL5 (5Bh)
          60. 7.28.2.4.60 LEDC_CTRL6 (5Ch)
          61. 7.28.2.4.61 LEDC_CTRL7 (5Dh)
          62. 7.28.2.4.62 LEDC_CTRL8 (5Eh)
          63. 7.28.2.4.63 LED_RAMP_UP_TIME (5Fh)
          64. 7.28.2.4.64 LED_RAMP_DOWN_TIME (60h)
          65. 7.28.2.4.65 LED_SEQ_EN (61h)
          66. 7.28.2.4.66 LEDx DC Current
          67. 7.28.2.4.67 LOADSWITCH (62h)
          68. 7.28.2.4.68 SPARE (63h)
          69. 7.28.2.4.69 VERNUM (64h)
  8. 8 Applications, Implementation, and Layout
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 DC-DC Converters
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Output Filter Design (Inductor and Output Capacitor)
            1. 8.2.1.2.1.1 Inductor Selection
            2. 8.2.1.2.1.2 Output Capacitor Selection
            3. 8.2.1.2.1.3 Input Capacitor Selection / Input Voltage
            4. 8.2.1.2.1.4 Output Capacitor Table
            5. 8.2.1.2.1.5 Voltage Change on DCDC1 to DCDC4
        3. 8.2.1.3 Application Curves
        4. 8.2.1.4 Layout
          1. 8.2.1.4.1 Layout Guidelines
          2. 8.2.1.4.2 Layout Example
    3. 8.3 Power Supply Recommendations
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
      2. 9.1.2 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Community Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
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订购信息

4 Pin Configuration and Functions

Figure 4-1 shows the 81-Pin YFF Die-Size Ball-Grid Array pin assignments.

TPS659121 TPS659122 ballout.gif Figure 4-1 81-Pin YFF DSBGA (Bottom View)

4.1 Pin Functions

Pin Functions

TERMINAL TYPE DESCRIPTION
NAME ALT NAME NO.
REFERENCE
VREF1V25 H3 O Internal reference voltage. Connect a 100-nF capacitor from this pin to GND. Do not load this pin externally.
AGND F3, C7 – Analog ground connection; connect to PGND on the PCB
DRIVERS / LIGHTING
LEDA/GPIO3 B3 I/O General-purpose I/O or LED driver output
LEDB/GPIO4 B2 I/O General-purpose I/O or LED driver output
LEDC/GPIO5 B1 I/O General-purpose I/O or LED driver output
STEP-DOWN CONVERTERS
VINDCDC_ANA C8 I Analog supply input for DC-DC converters; must be connected to VINDCDC1, VINDCDC2, VINDCDC3 and VINDCDC4
VINDCDC1 H7, J7 I Power input to DCDC1 converter; connect to VINDCDC2, VINDCDC3, VINDCDC4 and VINDCDC_ANA
VDCDC1 J4 I Voltage sense (feedback) input "+" for DCDC1
VDCDC1_GND H4 I Voltage sense (feedback) input GND for DCDC1; tie to the GND plane or to AGND, alternatively tie to the GND-pad of the output capacitor
SW1 H6, J6 O Switch node of DCDC1; connect output inductor
PGND1 H5, J5 – Power GND connection for DCDC1 converter
VCON_PWM F4 I PWM period signal for dynamic voltage scaling on DCDC1
VCON_CLK F5 I Clock signal for dynamic voltage scaling on DCDC1
VINDCDC2 C9 I Power input to DCDC2 converter; connect to VINDCDC1, VINDCDC3, VINDCDC4 and VINDCDC_ANA
VDCDC2 D7 I Voltage sense (feedback) input for DCDC2
SW2 D9 O Switch node of DCDC2; connect output inductor
PGND2 E9 – Power GND connection for DCDC2 converter
VINDCDC3 C1 I Power input to DCDC3 converter; connect to VINDCDC1, VINDCDC2, VINDCDC4 and VINDCDC_ANA
VDCDC3 F2 I Voltage sense (feedback) input for DCDC3
SW3 D1 O Switch node of DCDC3; connect output inductor
PGND3 E1 – Power GND connection for DCDC3 converter
VINDCDC4 A7, B7 I Power input to DCDC4 converter; connect to VINDCDC1, VINDCDC2, VINDCDC3 and VINDCDC_ANA
VDCDC4 A4 I Voltage sense (feedback) input "+" for DCDC4
VDCDC4_GND B4 I Voltage sense (feedback) input GND for DCDC4; tie to the GND plane or to AGND, alternatively tie to the GND-pad of the output capacitor
SW4 A6, B6 O Switch node of DCDC4; connect output inductor
PGND4 A5, B5 – Power GND connection for DCDC4 converter
LOAD SWITCH
LSI B8, B9 I Input of the load switch
LSO A8, A9 O Output of the load switch
EN_LS0 C3 I Load switch enable pin; the status is copied to Bit [LOADSWITCH:ENABLE0] in state CONFIG
EN_LS1 C2 I Load switch enable pin; the status is copied to Bit [LOADSWITCH:ENABLE1] in state CONFIG
LOW DROPOUT REGULATORS
VINLDO1210 J2 I Power input for LDO1, LDO2 and LDO10
VINLDO3 F8 I Power input for LDO3
VINLDO4 F1 I Power input for LDO4
VINLDO5 G8 I Power input for LDO5
VINLDO67 A2 I Power input for LDO6 and LDO7
VINLDO8 H8 I Power input for LDO8
VINLDO9 J8 I Power input for LDO9
LDOAO G3 O "LDO always on" internal supply; connect buffer capacitor
VLDO1 J3 O LDO1 output
VLDO2 H1 O LDO2 output
VLDO3 F9 O LDO3 output
VLDO4 G1 O LDO4 output
VLDO5 G9 O LDO5 output
VLDO6 A3 O LDO6 output
VLDO7 A1 O LDO7 output
VLDO8 H9 O LDO8 output
VLDO9 J9 O LDO9 output
VLDO10 J1 O LDO10 output
STANDARD INTERFACE
DEF_SPI_I2C-GPIO E7 I Digital input that defines whether SPI or I2C and GPIOs is available on pins C4, D4, E4, D5: 0=SPI; 1=I2C and GPIO1 and GPIO2
SCL_SCK SCK D5 I I2C SCL for DEF_SPI_I2C=1 or SPI SCK for DEF_SPI_I2C=0
SDA_MOSI MOSI E4 I/O I2C SDA for DEF_SPI_I2C=1 or SPI MASTER OUT SLAVE IN (MOSI) for DEF_SPI_I2C=0
GPIO1_MISO MISO D4 I/O GPIO1 for DEF_SPI_I2C=1 or SPI MASTER IN SLAVE OUT (MISO) for DEF_SPI_I2C=0
GPIO2_ CE CE C4 I/O GPIO2 for DEF_SPI_I2C=1 or SPI CHIP ENABLE (CE) active HIGH for DEF_SPI_I2C=0
ENABLE / VOLTAGE SCALING
EN1 / DCDC1_SEL(1) DCDC1_SEL E8 I Enable pin or voltage scaling pin changing the output of a converter or a group of converters between 2 predefined values
EN2 / DCDC2_SEL(1) DCDC2_SEL D8 I Enable pin or voltage scaling pin changing the output of a converter or a group of converters between 2 predefined values
EN3 / DCDC3_SEL(1) DCDC3_SEL C6 I Enable pin or voltage scaling pin changing the output of a converter or a group of converters between 2 predefined values
EN4 / DCDC4_SEL(1) DCDC4_SEL C5 I Enable pin or voltage scaling pin changing the output of a converter or a group of converters between 2 predefined values
SCL_AVS / CLK_REQ1(2) CLK_REQ1 E5 I Power I2C for dynamic voltage scaling: clock pin or clock request signal1 used to enable and disable power resources
SDA_AVS / CLK_REQ2(2) CLK_REQ2 E6 I/O Power I2C for dynamic voltage scaling; data pin or clock request signal2 used to enable and disable power resources
SLEEP / PWR_REQ(2) PWR_REQ G4 I SLEEP mode input or CLK request input
nRESPWRON / VSUP_OUT VSUP_OUT G6 O Reset output or output of voltage monitor
VCCS / VIN_MON VIN_MON G2 I Voltage sense for input voltage monitor; output on pin VSUP_OUT
PWRHOLD_ON ON D6 I POWERHOLD or ON; enable input
INT1 G5 O Interrupt output
nPWRON /RESIN (optional) D3 I Active low, debounced power-on input or power-request input to start power-up sequencing; alternatively active-low reset input to TPS65912x; debounced by 10 ms (OTP option); tie to LDOAO for a logic high if not used.
OMAP_WDI_32k_OUT F6 I Input from OMAP WDI pin to AND gate; alternatively 32-kHz RC oscillator output
CPCAP_WDI G7 O Push-pull output at VDDIO level of AND gate; connect to CPCAP WDI input
CONFIG1 E2 I Selects predefined startup options and default voltages; chooses from two internal OTP settings; tie to GND or LDOAO
CONFIG2 D2 I Selects predefined startup options; configures pins as DCDC1_SEL, DCDC2_SEL, DCDC3_SEL and DCDC4_SEL as well as CLK_REQ and PWR_REQ signals with CONFIG2 tied to GND. Tie to LDOAO for a logic high level.
VCC H2 I Digital supply input
VDDIO F7 I Supply voltage input for GPIOs and output stages that sets the HIGH level voltage (I/O voltage)
DGND E3 – Digital GND connection, tie to AGND and PGNDx on the PCB
(1) DCDCx_SEL is selected by pulling pin CONFIG2 to GND; this also selects CLK_REQx and PWR_REQ as enable resources.
(2) CLK-REQ1, CLK_REQ2 and PWR_REQ is selected by puling pin CONFIG2 to GND.
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