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ZHCSGJ3D July 2015 – February 2019 TPS65917-Q1

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5.3.7 Reset Levels

The TPS65917-Q1 resource control registers are defined by the following three categories:

Power-on request (POR) registers
Hardware (HW) registers
Switchoff (SWO) registers

These registers are associated to three levels of reset which are described as follows

Power-on reset (POR)

A POR occurs when the device receives supplies and transition from the NO SUPPLY state to the BACKUP state. The POR is the global device reset which resets all registers.

The values of the registers in this domain will retain their value under HWRST and SWORST event. This ensures the information which contains the cause of the switch off event is retained when the device is reset to its default operating state.

The following registers are reset only during POR event:

SMPS_THERMAL_STATUS
SMPS_SHORT_STATUS
SMPS_POWERGOOD_MASK
LDO_SHORT_STATUS
SWOFF_STATUS

This list is indicative only; a full list and bit details can be found in the TPS65917-Q1 Register Map (SLVUAH1).

Hardware reset (HWRST)

A HWRST occurs when any OFF request is configured to generate a hardware reset. Configuration of the reset level is programmed in the SWOFF_HWRST register. This reset triggers a transition to the OFF state from either the ACTIVE or SLEEP state, and therefore executes the ACT2OFF or SLP2OFF sequence.

A HWRST will reset all registers in the HWRST and the SWORST domain, but leave the registers in the POR domain unchanged.

The following registers are in the HWRST domain:

SMPS control registers expect MODE_ACTIVE and MODE_SLEEP bits
LDO control registers expect MODE_ACTIVE and MODE_SLEEP bits
VSYS_LO Threshold
PMU_CONFIG & PMU_CTRL
NSLEEP, ENABLE1, and ENABLE2 resource assignment registers
Input and Output, including the GPIO pins, Configuration and Control registers
Interrupt Control, Status and Mask Registers
OTP CRC results register
GPADC Configuration and Results registers

This list is indicative only; a full list and bit details can be found in the TPS65917-Q1 Register Map (SLVUAH1).

Switch-off reset (SWORST)

A SWORST occurs when any OFF request is configured to not generate a hardware reset. Configuration is done in the SWOFF_HWRST register. This reset acts like the HWRST, except only the SWO registers are reset. The TPS65917-Q1 goes into the OFF state, from either ACTIVE or SLEEP, and therefore executes the ACT2OFF or SLP2OFF sequence.

A SWORST only resets registers in the SWORST domain, but leave the registers in the HWRST and POR domains unchanged.

The following registers are in the SWORST domain:

SMPS control registers for voltage levels and operating mode control
LDO control registers for voltage levels and operating mode control
DEV_CTRL & POWER_CTRL registers
VSYS_MON enable and result register
WATCHDOG configuration register
PLL and REGEN Control registers

This list is indicative only; a full list and bit details can be found in the TPS65917-Q1 Register Map (SLVUAH1).

Table 5-7 lists the reset levels, and Figure 5-9 shows the reset levels versus registers.

Table 5-7 Reset Levels

LEVEL	RESET TAG	REGISTERS AFFECTED	COMMENT
0	POR	POR, HW, SWO	This reset level is the lowest level, for which all registers are reset.
1	HWRST	HW, SWO	During hardware reset (HWRST), all registers are reset except the POR registers.
2	SWORST	SWO	Only the SWO registers are reset.

Figure 5-9 Reset Levels versus Registers