5.4.1.2 Clock Generation for SMPS

In PWM mode, the SMPSs are synchronized on an external input clock, SYNCDCDC (muxed with GPIO_3), whereas in ECO mode, the switching frequency is based on an internal RC oscillator.

For PWM mode, a PLL is present to buffer the external clock input from SYNCDCDC pin, and to create 5 clock signals for the 5 SMPSs with different phases.

Figure 5-10 shows the frequency of SYNCDCDC input clock (f_SYNC) and the frequency of PLL output signal (f_SW).

Figure 5-10 Synchronized Clock Frequency

When no clock is present on the SYNCDCDC pin, the PLL generates a clock with a frequency equal to the fallback frequency (f_FALLBACK).

When a clock is present on the SYNCDCDC pin with a frequency between the low and high PLL saturation frequencies (f_SAT,LO and f_SAT,HI), then the PLL is synchronized on the SYNCDCDC clock and generates a clock with frequency equal to f_SYNC.

If f_SYNC is higher than f_SAT,HI, then the PLL generates a clock with a frequency equal to f_SAT,HI.

If f_SYNC is smaller than f_SAT,LO, then the PLL generates a clock with a frequency equal to f_SAT,LO.

Dithering can be achieved by changing the frequency of the clock provided on the SYNCDCDC pin. The sync clock dither specification parameters are based on a triangular dither pattern, but other patterns that comply with the minimum and maximum sync frequency range and the maximum dither slope can also be used, as seen in Figure 5-11.

Figure 5-11 Synchronized Clock Frequency Range and Dither