ZHCSNX8B December   2020  – September 2023 TPS6593-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
    1.     5
  5. 4 Revision History
  6. 5 说明（续）
  7. 6 Pin Configuration and Functions
    1. 6.1 Digital Signal Descriptions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  General Purpose Low Drop-Out Regulators (LDO1, LDO2, LDO3)
    6. 7.6  Low Noise Low Drop-Out Regulator (LDO4)
    7. 7.7  Internal Low Drop-Out Regulators (LDOVRTC, LDOVINT)
    8. 7.8  BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators
    9. 7.9  Reference Generator (BandGap)
    10. 7.10 Monitoring Functions
    11. 7.11 Clocks, Oscillators, and PLL
    12. 7.12 Thermal Monitoring and Shutdown
    13. 7.13 System Control Thresholds
    14. 7.14 Current Consumption
    15. 7.15 Backup Battery Charger
    16. 7.16 Digital Input Signal Parameters
    17. 7.17 Digital Output Signal Parameters
    18. 7.18 I/O Pullup and Pulldown Resistance
    19. 7.19 I2C Interface
    20. 7.20 Serial Peripheral Interface (SPI)
    21. 7.21 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  System Supply Voltage Monitor
      2. 8.3.2  Power Resources (Bucks and LDOs)
        1. 8.3.2.1 Buck Regulators
          1. 8.3.2.1.1  BUCK Regulator Overview
          2. 8.3.2.1.2  Multi-Phase Operation and Phase-Adding or Shedding
          3. 8.3.2.1.3  Transition Between PWM and PFM Modes
          4. 8.3.2.1.4  Multi-Phase BUCK Regulator Configurations
          5. 8.3.2.1.5  Spread-Spectrum Mode
          6. 8.3.2.1.6  Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support
          7. 8.3.2.1.7  BUCK Output Voltage Setting
          8. 8.3.2.1.8  BUCK Regulator Current Limit
          9. 8.3.2.1.9  SW_Bx Short-to-Ground Detection
          10. 8.3.2.1.10 Sync Clock Functionality
          11.        49
        2. 8.3.2.2 Low Dropout Regulators (LDOs)
          1. 8.3.2.2.1 LDOVINT
          2. 8.3.2.2.2 LDOVRTC
          3. 8.3.2.2.3 LDO1, LDO2, and LDO3
          4. 8.3.2.2.4 Low-Noise LDO (LDO4)
      3. 8.3.3  Output Voltage Monitor and PGOOD Generation
      4. 8.3.4  Thermal Monitoring
        1. 8.3.4.1 Thermal Warning Function
        2. 8.3.4.2 Thermal Shutdown
      5. 8.3.5  Backup Supply Power-Path
      6. 8.3.6  General-Purpose I/Os (GPIO Pins)
      7. 8.3.7  nINT, EN_DRV, and nRSTOUT Pins
      8. 8.3.8  Interrupts
      9. 8.3.9  RTC
        1. 8.3.9.1 General Description
        2. 8.3.9.2 Time Calendar Registers
          1. 8.3.9.2.1 TC Registers Read Access
          2. 8.3.9.2.2 TC Registers Write Access
        3. 8.3.9.3 RTC Alarm
        4. 8.3.9.4 RTC Interrupts
        5. 8.3.9.5 RTC 32-kHz Oscillator Drift Compensation
      10. 8.3.10 Watchdog (WDOG)
        1. 8.3.10.1 Watchdog Fail Counter and Status
        2. 8.3.10.2 Watchdog Start-Up and Configuration
        3. 8.3.10.3 MCU to Watchdog Synchronization
        4. 8.3.10.4 Watchdog Disable Function
        5. 8.3.10.5 Watchdog Sequence
        6. 8.3.10.6 Watchdog Trigger Mode
        7. 8.3.10.7 WatchDog Flow Chart and Timing Diagrams in Trigger Mode
        8.       79
        9. 8.3.10.8 Watchdog Question-Answer Mode
          1. 8.3.10.8.1 Watchdog Q&A Related Definitions
          2. 8.3.10.8.2 Question Generation
          3. 8.3.10.8.3 Answer Comparison
            1. 8.3.10.8.3.1 Sequence of the 2-bit Watchdog Answer Counter
            2. 8.3.10.8.3.2 Watchdog Sequence Events and Status Updates
            3. 8.3.10.8.3.3 Watchdog Q&A Sequence Scenarios
      11. 8.3.11 Error Signal Monitor (ESM)
        1. 8.3.11.1 ESM Error-Handling Procedure
          1. 8.3.11.1.1 Level Mode
          2.        90
          3. 8.3.11.1.2 PWM Mode
            1. 8.3.11.1.2.1 Good-Events and Bad-Events
            2. 8.3.11.1.2.2 ESM Error-Counter
            3. 8.3.11.1.2.3 ESM Start-Up in PWM Mode
            4. 8.3.11.1.2.4 ESM Flow Chart and Timing Diagrams in PWM Mode
            5.         96
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device State Machine
        1. 8.4.1.1 Fixed Device Power FSM
          1. 8.4.1.1.1 Register Resets and NVM Read at INIT State
        2. 8.4.1.2 Pre-Configurable Mission States
          1. 8.4.1.2.1 PFSM Commands
            1. 8.4.1.2.1.1  REG_WRITE_IMM Command
            2. 8.4.1.2.1.2  REG_WRITE_MASK_IMM Command
            3. 8.4.1.2.1.3  REG_WRITE_MASK_PAGE0_IMM Command
            4. 8.4.1.2.1.4  REG_WRITE_BIT_PAGE0_IMM Command
            5. 8.4.1.2.1.5  REG_WRITE_WIN_PAGE0_IMM Command
            6. 8.4.1.2.1.6  REG_WRITE_VOUT_IMM Command
            7. 8.4.1.2.1.7  REG_WRITE_VCTRL_IMM Command
            8. 8.4.1.2.1.8  REG_WRITE_MASK_SREG Command
            9. 8.4.1.2.1.9  SREG_READ_REG Command
            10. 8.4.1.2.1.10 SREG_WRITE_IMM Command
            11. 8.4.1.2.1.11 WAIT Command
            12. 8.4.1.2.1.12 DELAY_IMM Command
            13. 8.4.1.2.1.13 DELAY_SREG Command
            14. 8.4.1.2.1.14 TRIG_SET Command
            15. 8.4.1.2.1.15 TRIG_MASK Command
            16. 8.4.1.2.1.16 END Command
          2. 8.4.1.2.2 Configuration Memory Organization and Sequence Execution
          3. 8.4.1.2.3 Mission State Configuration
          4. 8.4.1.2.4 Pre-Configured Hardware Transitions
            1. 8.4.1.2.4.1 ON Requests
            2. 8.4.1.2.4.2 OFF Requests
            3. 8.4.1.2.4.3 NSLEEP1 and NSLEEP2 Functions
            4. 8.4.1.2.4.4 WKUP1 and WKUP2 Functions
            5. 8.4.1.2.4.5 LP_WKUP Pins for Waking Up from LP STANDBY
        3. 8.4.1.3 Error Handling Operations
          1. 8.4.1.3.1 Power Rail Output Error
          2. 8.4.1.3.2 Catastrophic Error
          3. 8.4.1.3.3 Watchdog (WDOG) Error
          4. 8.4.1.3.4 Warnings
        4. 8.4.1.4 Device Start-up Timing
        5. 8.4.1.5 Power Sequences
        6. 8.4.1.6 First Supply Detection
        7. 8.4.1.7 Register Power Domains and Reset Levels
      2. 8.4.2 Multi-PMIC Synchronization
        1. 8.4.2.1 SPMI Interface System Setup
        2. 8.4.2.2 Transmission Protocol and CRC
          1. 8.4.2.2.1 Operation with Transmission Errors
          2. 8.4.2.2.2 Transmitted Information
        3. 8.4.2.3 SPMI Target Device Communication to SPMI Controller Device
          1. 8.4.2.3.1 Incomplete Communication from SPMI Target Device to SPMI Controller Device
        4. 8.4.2.4 SPMI-BIST Overview
          1. 8.4.2.4.1 SPMI Bus during Boot BIST and RUNTIME BIST
          2. 8.4.2.4.2 Periodic Checking of the SPMI
          3. 8.4.2.4.3 SPMI Message Priorities
    5. 8.5 Control Interfaces
      1. 8.5.1 CRC Calculation for I2C and SPI Interface Protocols
      2. 8.5.2 I2C-Compatible Interface
        1. 8.5.2.1 数据有效性
        2. 8.5.2.2 启动和停止条件
        3. 8.5.2.3 Transferring Data
        4. 8.5.2.4 Auto-Increment Feature
      3. 8.5.3 Serial Peripheral Interface (SPI)
    6. 8.6 Configurable Registers
      1. 8.6.1 Register Page Partitioning
      2. 8.6.2 CRC Protection for Configuration, Control, and Test Registers
      3. 8.6.3 CRC Protection for User Registers
      4. 8.6.4 Register Write Protection
        1. 8.6.4.1 Watchdog and ESM Configuration Registers
        2. 8.6.4.2 User Registers
    7. 8.7 Register Maps
      1. 8.7.1 TPS6593-Q1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Powering a Processor
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 VCCA
          2. 9.2.1.2.2 Internal LDOs
          3. 9.2.1.2.3 Crystal Oscillator
          4. 9.2.1.2.4 Buck Input Capacitors
          5. 9.2.1.2.5 Buck Output Capacitors
          6. 9.2.1.2.6 Buck Inductors
          7. 9.2.1.2.7 LDO Input Capacitors
          8. 9.2.1.2.8 LDO Output Capacitors
          9. 9.2.1.2.9 Digital Signal Connections
      2. 9.2.2 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 第三方米6体育平台手机版_好二三四免责声明
    2. 10.2 Device Nomenclature
    3. 10.3 Documentation Support
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 支持资源
    6. 10.6 Trademarks
    7. 10.7 静电放电警告
    8. 10.8 术语表
  12. 11Mechanical, Packaging, and Orderable Information

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8.3.10.8.3.3 Watchdog Q&A Sequence Scenarios
Table 8-10 Correct and Incorrect WD Q&A Sequence Run Scenarios
NUMBER OF WD ANSWERSACTIONWD STATUS BITS IN WDT_STATUS REGISTERCOMMENTS
RESPONSE
WINDOW 1		RESPONSE
WINDOW 2		ANSW_ERRANSW_EARLYSEQ_ERRTIME_OUT
0 answers0 answers-New WD cycle starts after the end of RESPONSE WINDOW 2
-Increment WD failure counter
-New WD cycle starts with the same WD question		0b0b1b1bNo answers
0 answers4 INCORRECT answers-New WD cycle starts after the 4th WD answer
-Increment WD failure counter
-New WD cycle starts with the same WD question		1b0b1b0bWD_ANSW_CNT[1:0] = 3
0 answers4 CORRECT answers-New WD cycle starts after the 4th WD answer
-Increment WD failure counter
-New WD cycle starts with the same WD question		0b0b1b0bWD_ANSW_CNT[1:0] = 3
0 answers1 CORRECT answer-New WD cycle starts after the end of RESPONSE WINDOW 2
-Increment WD failure counter
-New WD cycle starts with the same WD question		0b0b1b1bLess than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3)
1 CORRECT answer1 CORRECT answer
2 CORRECT answer1 CORRECT answer
0 answers1 INCORRECT answer-New WD cycle starts after the end of RESPONSE WINDOW 2
-Increment WD failure counter
-New WD cycle starts with the same WD question		1b0b1b1bLess than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3)
1 CORRECT answer1 INCORRECT answer
2 CORRECT answers1 INCORRECT answer
0 answers4 CORRECT answers-New WD cycle starts after the 4th WD answer
-Increment WD failure counter
-New WD cycle starts with the same WD question		0b0b1b0bLess than 3 CORRECT ANSWER in WIN1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3)
1 CORRECT answer3 CORRECT answers
2 CORRECT answers2 CORRECT answers
0 answers4 INCORRECT answers-New WD cycle starts after the 4th WD answer
-Increment WD failure counter
-New WD cycle starts with the same WD question		1b0b1b0bLess than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3)
1 CORRECT answer3 INCORRECT answers
2 CORRECT answers2 INCORRECT answers
0 answers3 CORRECT answers-New WD cycle starts after the end of RESPONSE WINDOW 2
-Increment WD failure counter
-New WD cycle starts with the same WD question		0b0b1b1bLess than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3)
1 INCORRECT answer2 CORRECT answers-New WD cycle starts after the end of RESPONSE WINDOW 2
-Increment WD failure counter
-New WD cycle starts with the same WD question		1b0b1b1b
2 INCORRECT answers1 CORRECT answer
0 answers3 INCORRECT answers-New WD cycle starts after the end of RESPONSE WINDOW 2
-Increment WD failure counter
-New WD cycle starts with the same WD question		1b0b1b1bLess than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3)
1 INCORRECT answer2 INCORRECT answer
2 INCORRECT answer1 INCORRECT answer
0 answers4 CORRECT answers-New WD cycle starts after the 4th WD answer
-Increment WD failure counter
-New WD cycle starts with the same WD question		0b0b1b0bLess than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3)
1 INCORRECT answer3 CORRECT answers1b0b1b0b
2 INCORRECT answers2 CORRECT answers
0 answers4 INCORRECT answers-New WD cycle starts after the 4th WD answer
-Increment WD failure counter
-New WD cycle starts with the same WD question		1b0b1b0bLess than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3)
1 INCORRECT answer3 INCORRECT answers
2 INCORRECT answers2 INCORRECT answers
3 CORRECT answers0 answers-New WD cycle starts after the end of RESPONSE WINDOW 2
-Increment WD failure counter
-New WD cycle starts with the same WD Question		0b0b0b1bLess than 4 CORRECT ANSW in RESPONSE WINDOW 1 and more than 0 ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3)
2 CORRECT answers0 answers0b0b1b1b
1 CORRECT answers0 answers
3 CORRECT answers1 CORRECT answer-New WD cycle starts after the 4th WD answer
-Decrement WD failure counter
-New WD cycle starts with a new WD question		0b0b0b0bCORRECT SEQUENCE
3 CORRECT answers1 INCORRECT answers-New WD cycle starts after the 4th WD answer
-Increment WD failure counter
-New WD cycle starts with the same WD question		1b0b0b0bWD_ANSW_CNT[1:0] = 3
3 INCORRECT answers0 answers-New WD cycle starts after the end of RESPONSE WINDOW 2
-Increment WD failure counter
-New WD cycle starts with the same WD question		1b0b0b1bWD_ANSW_CNT[1:0] < 3
3 INCORRECT answers1 CORRECT answer-New WD cycle starts after the 4th WD answer
-Increment WD failure counter
-New WD cycle starts with the same WD question		1b0b0b0bWD_ANSW_CNT[1:0] = 3
3 INCORRECT answers1 INCORRECT answer-New WD cycle starts after the 4th WD answer
-Increment WD failure counter
-New WD cycle starts with the same WD question		1b0b0b0bWD_ANSW_CNT[1:0] = 3
4 CORRECT answersNot applicable-New WD cycle starts after the 4th WD answer
-Increment WD failure counter
-New WD cycle starts with the same WD question		0b1b0b0b4 CORRECT or INCORRECT ANSWER in RESPONSE WINDOW 1
3 CORRECT answers + 1 INCORRECT answerNot applicable-New WD cycle starts after the 4th WD answer
-Increment WD failure counter
-New WD cycle starts with the same WD question		1b1b0b0b
2 CORRECT answers + 2 INCORRECT answersNot applicable
1 CORRECT answer + 3 INCORRECT answersNot applicable
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