When the device arrives at a mission state, all rail sequencing is controlled by the pre-configurable FSM engine (PFSM) through the configuration memory. The configuration memory allows configurations of the triggers and the operation states that together form the configurable sub state machine within the scope of mission states. This sub state machine can be used to control and sequence the different voltage outputs as well as any GPIO outputs that can be used as enable for external rails. When the device is in a mission state, it has the capacity to supply the processor and other platform modules depending on the power rail configuration. The definitions and transition triggers of the mission states are configurable through the NVM configuration. Unlike the user registers, the PFSM definition stored in the NVM cannot be modified during normal operation. When the PMIC determines that a transition to another operation state is necessary, it reads the configuration memory to determine what sequencing is needed for the state transition. Furthermore, the PFSM has four storage registers, further referred to as PFSM storage registers (R0-3).

Table 8-15 shows how the trigger signals for each state transition can come from a variety of interface or GPIO inputs, or potential error sources. Figure 8-37 shows how the device processes all of the possible error sources inside the PFSM engine, a hierarchical mask system is applied to filter out the common errors that can be handled by interrupt only, and categorize the other error sources as Severe Global Error, Moderate Global Error, and so forth. The filtered and categorized triggers are sent into the PFSM engine, that then determines the entry and exit condition for each configured mission state.

Figure 8-37 Error Source Hierarchical Mask System

Figure 8-39 shows an example of how the PFSM engine utilizes instructions to execute the configured device state and sequence transitions of the mission state-machine. Table 8-12 provides the instruction set and usage description of each instruction in the following sections. Section 8.4.1.2.2 describes how the instructions are stored in the NVM memory.