The device supports SPI serial-bus interface and it operates as a peripheral device. The MCU in the system acts as the controller device. A single read and write transmission consists of 24-bit write and read cycles (32-bit if CRC is enabled) in the following order:

• Bits 1-8: ADDR[7:0], Register address
• Bits 9-11: PAGE[2:0], Page address for register
• Bit 12: Read/Write definition, 0 = WRITE, 1 = READ.
• Bits 13-16: RESERVED[4:0], Reserved, use all zeros.
• For Write: Bits 17-24: WDATA[7:0], write data
• For Write with CRC enabled: Bits 25-32: R_CRC[7:0], CRC error code calculated from bits 1-24 sent by the controller device (the MCU). See Section 8.5.1.
• For Read: Bits 17-24: RDATA[7:0], read data
• For Read with CRC enabled: Bits 25-32: T_CRC[7:0], CRC error code calculated from bits 1-16 sent by the controller device (the MCU), and bits 17-24, sent by the peripheral device (the TPS6593-Q1). See Section 8.5.1.

The embedded CRC filed can be enabled or deactivated from the protocol by setting the I2C1_SPI_CRC_EN register bit to '1' - enabled, '0' - deactivated. The default of this bit is configurable through the NVM.

The SDO output is in a high-impedance state when the CS pin is high. When the CS pin is low, the SDO output is always driven low except when the RDATA or SCRC bits are sent. When the RDATA or SCRC bits are sent, the SDO output is driven accordingly.

The address, page, data, and CRC are transmitted MSB first. The chip-select signal (CS) must be low during the cycle transmission. The CS signal resets the interface when it is high, and must be taken high between successive cycles. Data is clocked in on the rising edge of the SCLK clock signal and it is clocked out on the falling edge of SCLK clock signal.

The SPI Timing diagram shows the timing information for these signals.

Figure 8-58 SPI Write Cycle

Figure 8-59 SPI Write Cycle with CRC

Figure 8-60 SPI Read Cycle

Figure 8-61 SPI Read Cycle with CRC