ZHCSNX8B December   2020  – September 2023 TPS6593-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
    1.     5
  5. 4 Revision History
  6. 5 说明（续）
  7. 6 Pin Configuration and Functions
    1. 6.1 Digital Signal Descriptions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  General Purpose Low Drop-Out Regulators (LDO1, LDO2, LDO3)
    6. 7.6  Low Noise Low Drop-Out Regulator (LDO4)
    7. 7.7  Internal Low Drop-Out Regulators (LDOVRTC, LDOVINT)
    8. 7.8  BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators
    9. 7.9  Reference Generator (BandGap)
    10. 7.10 Monitoring Functions
    11. 7.11 Clocks, Oscillators, and PLL
    12. 7.12 Thermal Monitoring and Shutdown
    13. 7.13 System Control Thresholds
    14. 7.14 Current Consumption
    15. 7.15 Backup Battery Charger
    16. 7.16 Digital Input Signal Parameters
    17. 7.17 Digital Output Signal Parameters
    18. 7.18 I/O Pullup and Pulldown Resistance
    19. 7.19 I2C Interface
    20. 7.20 Serial Peripheral Interface (SPI)
    21. 7.21 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  System Supply Voltage Monitor
      2. 8.3.2  Power Resources (Bucks and LDOs)
        1. 8.3.2.1 Buck Regulators
          1. 8.3.2.1.1  BUCK Regulator Overview
          2. 8.3.2.1.2  Multi-Phase Operation and Phase-Adding or Shedding
          3. 8.3.2.1.3  Transition Between PWM and PFM Modes
          4. 8.3.2.1.4  Multi-Phase BUCK Regulator Configurations
          5. 8.3.2.1.5  Spread-Spectrum Mode
          6. 8.3.2.1.6  Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support
          7. 8.3.2.1.7  BUCK Output Voltage Setting
          8. 8.3.2.1.8  BUCK Regulator Current Limit
          9. 8.3.2.1.9  SW_Bx Short-to-Ground Detection
          10. 8.3.2.1.10 Sync Clock Functionality
          11.        49
        2. 8.3.2.2 Low Dropout Regulators (LDOs)
          1. 8.3.2.2.1 LDOVINT
          2. 8.3.2.2.2 LDOVRTC
          3. 8.3.2.2.3 LDO1, LDO2, and LDO3
          4. 8.3.2.2.4 Low-Noise LDO (LDO4)
      3. 8.3.3  Output Voltage Monitor and PGOOD Generation
      4. 8.3.4  Thermal Monitoring
        1. 8.3.4.1 Thermal Warning Function
        2. 8.3.4.2 Thermal Shutdown
      5. 8.3.5  Backup Supply Power-Path
      6. 8.3.6  General-Purpose I/Os (GPIO Pins)
      7. 8.3.7  nINT, EN_DRV, and nRSTOUT Pins
      8. 8.3.8  Interrupts
      9. 8.3.9  RTC
        1. 8.3.9.1 General Description
        2. 8.3.9.2 Time Calendar Registers
          1. 8.3.9.2.1 TC Registers Read Access
          2. 8.3.9.2.2 TC Registers Write Access
        3. 8.3.9.3 RTC Alarm
        4. 8.3.9.4 RTC Interrupts
        5. 8.3.9.5 RTC 32-kHz Oscillator Drift Compensation
      10. 8.3.10 Watchdog (WDOG)
        1. 8.3.10.1 Watchdog Fail Counter and Status
        2. 8.3.10.2 Watchdog Start-Up and Configuration
        3. 8.3.10.3 MCU to Watchdog Synchronization
        4. 8.3.10.4 Watchdog Disable Function
        5. 8.3.10.5 Watchdog Sequence
        6. 8.3.10.6 Watchdog Trigger Mode
        7. 8.3.10.7 WatchDog Flow Chart and Timing Diagrams in Trigger Mode
        8.       79
        9. 8.3.10.8 Watchdog Question-Answer Mode
          1. 8.3.10.8.1 Watchdog Q&A Related Definitions
          2. 8.3.10.8.2 Question Generation
          3. 8.3.10.8.3 Answer Comparison
            1. 8.3.10.8.3.1 Sequence of the 2-bit Watchdog Answer Counter
            2. 8.3.10.8.3.2 Watchdog Sequence Events and Status Updates
            3. 8.3.10.8.3.3 Watchdog Q&A Sequence Scenarios
      11. 8.3.11 Error Signal Monitor (ESM)
        1. 8.3.11.1 ESM Error-Handling Procedure
          1. 8.3.11.1.1 Level Mode
          2.        90
          3. 8.3.11.1.2 PWM Mode
            1. 8.3.11.1.2.1 Good-Events and Bad-Events
            2. 8.3.11.1.2.2 ESM Error-Counter
            3. 8.3.11.1.2.3 ESM Start-Up in PWM Mode
            4. 8.3.11.1.2.4 ESM Flow Chart and Timing Diagrams in PWM Mode
            5.         96
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device State Machine
        1. 8.4.1.1 Fixed Device Power FSM
          1. 8.4.1.1.1 Register Resets and NVM Read at INIT State
        2. 8.4.1.2 Pre-Configurable Mission States
          1. 8.4.1.2.1 PFSM Commands
            1. 8.4.1.2.1.1  REG_WRITE_IMM Command
            2. 8.4.1.2.1.2  REG_WRITE_MASK_IMM Command
            3. 8.4.1.2.1.3  REG_WRITE_MASK_PAGE0_IMM Command
            4. 8.4.1.2.1.4  REG_WRITE_BIT_PAGE0_IMM Command
            5. 8.4.1.2.1.5  REG_WRITE_WIN_PAGE0_IMM Command
            6. 8.4.1.2.1.6  REG_WRITE_VOUT_IMM Command
            7. 8.4.1.2.1.7  REG_WRITE_VCTRL_IMM Command
            8. 8.4.1.2.1.8  REG_WRITE_MASK_SREG Command
            9. 8.4.1.2.1.9  SREG_READ_REG Command
            10. 8.4.1.2.1.10 SREG_WRITE_IMM Command
            11. 8.4.1.2.1.11 WAIT Command
            12. 8.4.1.2.1.12 DELAY_IMM Command
            13. 8.4.1.2.1.13 DELAY_SREG Command
            14. 8.4.1.2.1.14 TRIG_SET Command
            15. 8.4.1.2.1.15 TRIG_MASK Command
            16. 8.4.1.2.1.16 END Command
          2. 8.4.1.2.2 Configuration Memory Organization and Sequence Execution
          3. 8.4.1.2.3 Mission State Configuration
          4. 8.4.1.2.4 Pre-Configured Hardware Transitions
            1. 8.4.1.2.4.1 ON Requests
            2. 8.4.1.2.4.2 OFF Requests
            3. 8.4.1.2.4.3 NSLEEP1 and NSLEEP2 Functions
            4. 8.4.1.2.4.4 WKUP1 and WKUP2 Functions
            5. 8.4.1.2.4.5 LP_WKUP Pins for Waking Up from LP STANDBY
        3. 8.4.1.3 Error Handling Operations
          1. 8.4.1.3.1 Power Rail Output Error
          2. 8.4.1.3.2 Catastrophic Error
          3. 8.4.1.3.3 Watchdog (WDOG) Error
          4. 8.4.1.3.4 Warnings
        4. 8.4.1.4 Device Start-up Timing
        5. 8.4.1.5 Power Sequences
        6. 8.4.1.6 First Supply Detection
        7. 8.4.1.7 Register Power Domains and Reset Levels
      2. 8.4.2 Multi-PMIC Synchronization
        1. 8.4.2.1 SPMI Interface System Setup
        2. 8.4.2.2 Transmission Protocol and CRC
          1. 8.4.2.2.1 Operation with Transmission Errors
          2. 8.4.2.2.2 Transmitted Information
        3. 8.4.2.3 SPMI Target Device Communication to SPMI Controller Device
          1. 8.4.2.3.1 Incomplete Communication from SPMI Target Device to SPMI Controller Device
        4. 8.4.2.4 SPMI-BIST Overview
          1. 8.4.2.4.1 SPMI Bus during Boot BIST and RUNTIME BIST
          2. 8.4.2.4.2 Periodic Checking of the SPMI
          3. 8.4.2.4.3 SPMI Message Priorities
    5. 8.5 Control Interfaces
      1. 8.5.1 CRC Calculation for I2C and SPI Interface Protocols
      2. 8.5.2 I2C-Compatible Interface
        1. 8.5.2.1 数据有效性
        2. 8.5.2.2 启动和停止条件
        3. 8.5.2.3 Transferring Data
        4. 8.5.2.4 Auto-Increment Feature
      3. 8.5.3 Serial Peripheral Interface (SPI)
    6. 8.6 Configurable Registers
      1. 8.6.1 Register Page Partitioning
      2. 8.6.2 CRC Protection for Configuration, Control, and Test Registers
      3. 8.6.3 CRC Protection for User Registers
      4. 8.6.4 Register Write Protection
        1. 8.6.4.1 Watchdog and ESM Configuration Registers
        2. 8.6.4.2 User Registers
    7. 8.7 Register Maps
      1. 8.7.1 TPS6593-Q1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Powering a Processor
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 VCCA
          2. 9.2.1.2.2 Internal LDOs
          3. 9.2.1.2.3 Crystal Oscillator
          4. 9.2.1.2.4 Buck Input Capacitors
          5. 9.2.1.2.5 Buck Output Capacitors
          6. 9.2.1.2.6 Buck Inductors
          7. 9.2.1.2.7 LDO Input Capacitors
          8. 9.2.1.2.8 LDO Output Capacitors
          9. 9.2.1.2.9 Digital Signal Connections
      2. 9.2.2 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 第三方米6体育平台手机版_好二三四免责声明
    2. 10.2 Device Nomenclature
    3. 10.3 Documentation Support
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 支持资源
    6. 10.6 Trademarks
    7. 10.7 静电放电警告
    8. 10.8 术语表
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.10 Monitoring Functions

Over operating free-air temperature range (unless otherwise noted). Voltage level is measured with reference to the thermal/ground pad of the device.
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Electrical Characteristics: BUCK REGULATORS OUTPUT
7.1a VBUCK_OV_TH Overvoltage monitoring for BUCK output, threshold accuracy, VOUT_Bn ≥ 1 V(1) BUCKn_OV_THR = 0x0 2% 3% 4%
7.1b BUCKn_OV_THR = 0x1 2.5% 3.5% 4.5%
7.1c BUCKn_OV_THR = 0x2 3% 4% 5%
7.1d BUCKn_OV_THR = 0x3 4% 5% 6%
7.1e BUCKn_OV_THR = 0x4 5% 6% 7%
7.1f BUCKn_OV_THR = 0x5 6% 7% 8%
7.1g BUCKn_OV_THR = 0x6 7% 8% 9%
7.1h BUCKn_OV_THR = 0x7 9% 10% 11%
7.2a VBUCK_OV_TH_mv  Overvoltage monitoring for BUCK output, threshold accuracy, VOUT_Bn < 1 V(1) BUCKn_OV_THR = 0x0 20 30 40 mV
7.2b BUCKn_OV_THR = 0x1 25 35 45
7.2c BUCKn_OV_THR = 0x2 30 40 50
7.2d BUCKn_OV_THR = 0x3 40 50 60
7.2e BUCKn_OV_THR = 0x4 50 60 70
7.2f BUCKn_OV_THR = 0x5 60 70 80
7.2g BUCKn_OV_THR = 0x6 70 80 90
7.2h BUCKn_OV_THR = 0x7 90 100 110
7.3a VBUCK_UV_TH  Undervoltage monitoring for buck output, threshold accuracy, VOUT_Bn  ≥ 1 V(1) BUCKn_UV_THR = 0x0 –4% –3% –2%
7.3b BUCKn_UV_THR = 0x1 –4.5% –3.5% –2.5%
7.3c BUCKn_UV_THR = 0x2 –5% –4% –3%
7.3d BUCKn_UV_THR = 0x3 –6% –5% –4%
7.3e BUCKn_UV_THR = 0x4 –7% –6% –5%
7.3f BUCKn_UV_THR = 0x5 –8% –7% –6%
7.3g BUCKn_UV_THR = 0x6 –9% –8% –7%
7.3h BUCKn_UV_THR = 0x7 –11% –10% –9%
7.4a VBUCK_UV_TH_mv  Undervoltage monitoring for buck output, threshold accuracy, VOUT_Bn < 1 V(1) BUCKn_UV_THR = 0x0 –40 –30 –20 mV
7.4b BUCKn_UV_THR = 0x1 –45 –35 –25
7.4c BUCKn_UV_THR = 0x2 –50 –40 –30
7.4d BUCKn_UV_THR = 0x3 –60 –50 –40
7.4e BUCKn_UV_THR = 0x4 –70 –60 –50
7.4f BUCKn_UV_THR = 0x5 –80 –70 –60
7.4g BUCKn_UV_THR = 0x6 –90 –80 –70
7.4h BUCKn_UV_THR = 0x7 –110 –100 –90
Electrical Characteristics: LDO REGULATOR OUTPUTS
7.5a VLDO_OV_TH Overvoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn ≥ 1 V(2) LDOn_OV_THR = 0x0 2% 3% 4%
7.5b LDOn_OV_THR = 0x1 2.5% 3.5% 4.5%
7.5c LDOn_OV_THR = 0x2 3% 4% 5%
7.5d LDOn_OV_THR = 0x3 4% 5% 6%
7.5e LDOn_OV_THR = 0x4 5% 6% 7%
7.5f LDOn_OV_THR = 0x5 6% 7% 8%
7.5g LDOn_OV_THR = 0x6 7% 8% 9%
7.5h LDOn_OV_THR = 0x7 9% 10% 11%
7.6a VLDO_OV_TH_mv Overvoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn < 1 V(2) LDOn_OV_THR = 0x0 20 30 40 mV
7.6b LDOn_OV_THR = 0x1 25 35 45
7.6c LDOn_OV_THR = 0x2 30 40 50
7.6d LDOn_OV_THR = 0x3 40 50 60
7.6e LDOn_OV_THR = 0x4 50 60 70
7.6f LDOn_OV_THR = 0x5 60 70 80
7.6g LDOn_OV_THR = 0x6 70 80 90
7.6h LDOn_OV_THR = 0x7 90 100 110
7.7a VLDO_UV_TH Undervoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn ≥ 1 V(2) LDOn_UV_THR = 0x0 –4% –3% –2%
7.7b LDOn_UV_THR = 0x1 –4.5% –3.5% –2.5%
7.7c LDOn_UV_THR = 0x2 –5% –4% –3%
7.7d LDOn_UV_THR = 0x3 –6% –5% –4%
7.7e LDOn_UV_THR = 0x4 –7% –6% –5%
7.7f LDOn_UV_THR = 0x5 –8% –7% –6%
7.7g LDOn_UV_THR = 0x6 –9% –8% –7%
7.7h LDOn_UV_THR = 0x7 –11% –10% –9%
7.8a VLDO_UV_TH_mv Undervoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn < 1 V(2) LDOn_UV_THR = 0x0 –40 –30 –20 mV
7.8b LDOn_UV_THR = 0x1 –45 –35 –25
7.8c LDOn_UV_THR = 0x2 –50 –40 –30
7.8d LDOn_UV_THR = 0x3 –60 –50 –40
7.8e LDOn_UV_THR = 0x4 –70 –60 –50
7.8f LDOn_UV_THR = 0x5 –80 –70 –60
7.8g LDOn_UV_THR = 0x6 –90 –80 –70
7.8h LDOn_UV_THR = 0x7 –110 –100 –90
Electrical Characteristics: VCCA INPUT
7.9a VCCAOV_TH Overvoltage monitoring for VCCA input, threshold accuracy(3) VCCA_OV_THR = 0x0 2% 3% 4%
7.9b VCCA_OV_THR = 0x1 2.5% 3.5% 4.5%
7.9c VCCA_OV_THR = 0x2 3% 4% 5%
7.9d VCCA_OV_THR = 0x3 4% 5% 6%
7.9e VCCA_OV_THR = 0x4 5% 6% 7%
7.9f VCCA_OV_THR = 0x5 6% 7% 8%
7.9g VCCA_OV_THR = 0x6 7% 8% 9%
7.9h VCCA_OV_THR = 0x7 9% 10% 11%
7.10a VCCAUV_TH Undervoltage monitoring for VCCA input, threshold accuracy(3) VCCA_UV_THR = 0x0 -4% -3% -2%
7.10b VCCA_UV_THR = 0x1 -4.5% -3.5% -2.5%
7.10c VCCA_UV_THR = 0x2 -5% -4% -3%
7.10d VCCA_UV_THR = 0x3 -6% -5% -4%
7.10e VCCA_UV_THR = 0x4 -7% -6% -5%
7.10f VCCA_UV_THR = 0x5 -8% -7% -6%
7.10g VCCA_UV_THR = 0x6 -9% -8% -7%
7.10h VCCA_UV_THR = 0x7 -11% -10% -9%
Timing Requirements
26.30a tdelay_OV_UV BUCK and LDO OV/UV detection delay Detection delay with 5 mV (Vin < 1 V) or 0.5% (Vin ≥ 1 V) over/underdrive 8 µs
26.30b tdelay_OV_UV VCCA OV/UV detection delay Detection delay with 30 mV over/underdrive 12 µs
26.31a tdeglitch1_OV_UV VCCA, BUCK and LDO OV/UV signal deglitch time VMON_DEGLITCH_SEL = 0: Digital deglitch time for detected signal 3.4 3.8 4.2 µs
26.31b tdeglitch2_OV_UV VMON_DEGLITCH_SEL = 1: Digital deglitch time for detected signal 18 20 22 µs
26.32a tlatency1_OV_UV BUCK and LDO OV/UV signal latency time VMON_DEGLITCH_SEL = 0: Total delay from 5mV (Vin < 1 V) or 0.5% (Vin ≥ 1 V) over/underdrive to interrupt or PFSM trigger 13 µs
26.32b tlatency2_OV_UV VMON_DEGLITCH_SEL = 1: Total delay from 5mV (Vin < 1 V) or 0.5% (Vin ≥ 1 V) over/underdrive to interrupt or PFSM trigger 30 µs
26.32b tlatency1_VCCA_OV_UV VCCA OV/UV signal latency time VMON_DEGLITCH_SEL = 0: Total delay from 30 mV over/underdrive to interrupt or PFSM trigger 13 µs
26.32b tlatency2_VCCA_OV_UV VMON_DEGLITCH_SEL = 1: Total delay from 30 mV over/underdrive to interrupt or PFSM trigger 30 µs
26.33a tdeglitch_PGOOD_rise PGOOD signal deglitch time Internal logic signal transitions from invalid to valid(4) 9.5 10.5 µs
26.33b tdeglitch_PGOOD_fall Internal logic signal transitions from valid to invalid(4) 0 µs
(1) The default values of BUCKn_OV_THR & BUCKn_UV_THR registers come from the NVM memory, and can be re-configured by software.
(2) The default values of LDOn_OV_THR & LDOn_UV_THR registers come from the NVM memory, and can be re-configured by software.
(3) The default values of VCCA_OV_THR & VCCA_UV_THR registers come from the NVM memory, and can be re-configured by software.
(4) Interrupt status signal is input signal for PGOOD deglitch logic.
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