ZHCSKK3B December 2019 – February 2022 TPS6594-Q1
PRODUCTION DATA
The Mission States portion of the FSM engine manages the sequencing of power rails and external outputs in the user defined states. For the rest of Section 8.4.1 the Figure 8-42 is used as an example state machine which is defined through the configuration memory using the configuration FSM instructions.
Each power state (light blue bubbles in Figure 8-42) defines the ON or OFF state and the sequencing timing of the external regulators and GPIO outputs. This example defines 4 power states: STANDBY, ACTIVE, MCU ONLY, and DEEP_SLEEP/S2R states. The priority order of these states is as follows:
The transitions between each power state is determined by the trigger signals source pre-selected from Table 8-15. These triggers are then placed in the order of priority through the trigger ID assignment of each trigger source. The critical error triggers are placed first, some specified as immediate triggers that can interrupt an on-going sequence. The non-error triggers, which are used to enable state transitions during normal device operation, are then placed according to the priority order of the state the device is transitioning to. Table 8-16 list the trigger signal sources, in the order of priority, used to define the power states and transitions of the example mission state machine shown in Figure 8-42. This table also helps to determine which triggers must be masked by the TRIG_MASK command upon arriving a pre-defined power state to produce the desired PFSM behavior.
Trigger ID | Trigger Signal | State Transitions | Trigger Masked In Each User Defined Power State | |||
---|---|---|---|---|---|---|
STANDBY | ACTIVE | MCU ONLY | DEEP SLEEP / S2R | |||
0 | IMMEDIATE_SHUTDOWN (1) | From any state to SAFE RECOVERY | ||||
1 | MCU_POWER_ERROR (1) | From any state to SAFE RECOVERY | ||||
2 | ORDERLY_SHUTDOWN (1) | From any state to SAFE RECOVERY | ||||
3 | TRIGGER_FORCE_STANDBY | From any state to STANDBY or LP_STANDBY | Masked | |||
4 | WD_ERROR | Perform warm reset of all power rails and return to ACTIVE | Masked | Masked | Masked | |
5 | ESM_MCU_ERROR | Perform warm reset of all power rails and return to ACTIVE | Masked | Masked | Masked | |
6 | ESM_SOC_ERROR | Perform warm reset of power rails in SOC domain and return to ACTIVE | Masked | Masked | Masked | |
7 | WD_ERROR | Perform warm reset of all power rails and return to MCU ONLY | Masked | Masked | Masked | |
8 | ESM_MCU_ERROR | Perform warm reset of all power rails and return to MCU ONLY | Masked | Masked | Masked | |
9 | SOC_POWER_ERROR | ACTIVE to MCU ONLY | Masked | Masked | Masked | |
10 | TRIGGER _I2C_1 (self-cleared) | Start RUNTIME_BIST | Masked | Masked | ||
11 | TRIGGER_I2C_2 (self-cleared) | Enable I2C CRC Function | Masked | Masked | ||
12 | TRIGGER_SU_ACTIVE | STANDBY to ACTIVE | Masked | Masked | ||
13 | TRIGGER_WKUP1 | Any State to ACTIVE | ||||
14 | TRIGGER_A (NSLEEP2&NSLEEP1 = '11') | MCU ONLY or DEEP SLEEP/S2R to ACTIVE | Masked | |||
15 | TRIGGER_SU_MCU_ONLY | STANDBY to MCU ONLY | Masked | Masked | ||
16 | TRIGGER_WKUP2 | STANDBY or DEEP SLEEP/S2R to MCU ONLY | Masked | |||
17 | TRIGGER_B (NSLEEP2&NSLEEP1 = '10') | ACTIVE or DEEP SLEEP/S2R to MCU ONLY | Masked | |||
18 | TRIGGER_D or TRIGGER_C (NSLEEP2 = '0' ) | ACTIVE or MCU ONLY to DEEP SLEEP/S2R | Masked | Masked | ||
19 | TRIGGER_I2C_0 (self-cleared) | Any state to STANDBY | Masked | Masked | ||
20 | Always '1' (2) | STANDBY to SAFE RECOVERY | Mask | Masked | Masked | Masked |
21 | Not Used | Mask | Masked | Masked | Masked | |
22 | Not Used | Mask | Masked | Masked | Masked | |
23 | Not Used | Mask | Masked | Masked | Masked | |
24 | Not Used | Mask | Masked | Masked | Masked | |
25 | Not Used | Mask | Masked | Masked | Masked | |
26 | Not Used | Mask | Masked | Masked | Masked | |
27 | Not Used | Mask | Masked | Masked | Masked | |
28-bit TRIG_MASK Value in Hex format: | 0xFFE4FF8 | 0xFF18180 | 0xFF01270 | 0xFFC9FF0 |