The TPS6594-Q1 device integrates a finite state machine (FSM) engine, which manages the state of the device during operating state transitions. It supports NVM-configurable mission states with configurable input triggers for transitions between states. Any resources, including the 5 BUCK regulators, 4 LDO regulators, and all of the digital IO pins including the 11 GPIO pins on the device can be controlled during power sequencing. When a resource is not controlled or configured through a power sequence, the resource is left in the default state as pre-configured by the NVM.

Each resource can be pre-configured through the NVM configuration, or re-configured through register bits. Therefore, the user can statically control the resource through the control interfaces (I²C or SPI), or the FSM can automatically control the resource during state sequences.

The FSM is powered by an internal LDO which is automatically enabled when VCCA supply is available to the device. Ensuring that the VCCA supply is the first supply available to the device is important to ensure proper operation of all the power resources as well as the control interface and device IOs.

There are 3 parts of the FSM which control the operational modes of the TPS6594-Q1 device:

• Fixed Device Power Finite State Machine (FFSM)
• Pre-configurable Finite State Machine (PFSM) for Mission States (ACTIVE, MCU_ONLY, S2R, DEEP_SLEEP)
• Error Handling Operations

The PFSM provides configurable rail and voltage monitoring sequencing utilizing instructions in configuration memory. This flexibility enables customers to alter power-up sequences on a platform basis. The FFSM handles the majority of fixed functionality that is internally mandated and common to all platforms.