ZHCSKK3B December 2019 – February 2022 TPS6594-Q1
PRODUCTION DATA
ON requests are used to switch on the device, which transitions the device from the STANDBY or the LP_STANDBY to the state specified by STARTUP_DEST[1:0].
After the device arrives at the corresponding STARTUP_DEST[1:0] operation state, the MCU must setup the NSLEEP1 and NSLEEP2 signals accordingly before clearing the STARTUP_INT interrupt. Once the interrupt is cleared, the device stays or moves to the next state corresponding to the NSLEEP signals state assignment as specified in Table 8-20.
Table 8-17 lists the available ON requests.
EVENT | MASKABLE | COMMENT | DEBOUNCE | |
---|---|---|---|---|
nPWRON (pin) | Yes | Edge sensitive | 50 ms | |
ENABLE (pin) | Yes | Level sensitive | 8 µs | |
First Supply Detection (FSD) | Yes | VCCA > VCCA_UV and FSD unmasked | N/A | |
RTC ALARM Interrupt | Yes | N/A | ||
RTC TIMER Interrupt | Yes | N/A | ||
WKUP1 or WKUP2 Detection | Yes | Edge sensitive | 8 µs | |
LP_WKUP1 or LP_WKUP2 Detection | Yes | Edge sensitive | N/A | |
Recovery from Immediate and Orderly Shutdown | Yes | Recover from system errors which caused immediate or orderly shutdown of the device | N/A |
If one of the events listed in Table 8-17 occurs, then the event powers on the device unless one of the gating conditions listed in Table 8-18 is present.
EVENT | MASKABLE | COMMENT | ||
---|---|---|---|---|
VCCA_OVP (event) | No | VCCA > VCCA_OVP, VSYS_DEAD_LOCK_EN = 1 | ||
VCCA_UVLO (event) | No | VCCA < VCCA_UVLO | ||
VINT_OVP (event) | No | LDOVINT > 1.98 V | ||
VINT_UVLO (event) | No | LDOVINT < 1.62 V | ||
TSD (event) | No | Device stays in SAFE RECOVERY until temperature decreases below TWARN level |
The NPWRON_SEL NVM register bit determines whether the nPWRON/ENABLE pin is treated as a power on press button or a level sensitive enable switch. When this pin is configured as the nPWRON button, a short button press detection is latched internally as a device enable signal until the NPWRON_START_INT is cleared, or a long press key event is detected. The short button press detection occurs when an falling edge is detected at the nPWRON pin. When the NPWRON_START_MASK bit is set to '1', the device does no longer react to the changing state of the pin as the nPWRON press button.
The nPWRON/ENABLE pin is a level sensitive pin when it is configured as an ENABLE pin, and an assertion enables the device until the pin is released. When the ENABLE_MASK bit is set to '1', the device does no longer react to the changing state of the pin as the ENABLE switch.