In Level Mode, after MCU has set the start bit (bit ESM_MCU_START or bit ESM_SOC_START), the ESM monitors its nERR_MCU or nERR_SoC input pin. Each ESM detects an ESM-error when the voltage level on its input pin remains low for a time equal or longer than the deglitch-time t_{degl_ESMx}. When an ESM_x detects an ESM-error, it starts the ESM Error-Handling procedure as described in Section 8.3.12.1. Section 8.3.12.1 describes how if the voltage level on its input pin remains high for a time equal or longer than the deglitch-time t_{degl_ESMx}, before the elapse of the configured delay-1 or delay-2 time-intervals, and the MCU software clears all ESM related interrupt bits, then the ESM-error is no longer present and the ESM stops the Error-Handling Procedure. If the ESM-error persists such that the configured delay-1 and delay-2 times elapse, the ESM sends a ESM_x_RST trigger to the PFSM and the device clear the ESM_x_START bit. After the PFSM completes the handling of the ESM_x_RST trigger, the device re-initializes the ESM.

For a complete overview on how the ESM works in Level Mode, please refer to the flow-chart in Figure 8-28. In this flow-chart, the _x stands for either _MCU or _SoC. Figure 8-29, Figure 8-30, Figure 8-31, and Figure 8-32 show example wave forms for several error-cases for the ESM in Level Mode. In these examples, only the ESM_MCU is shown.

Figure 8-28 Flow Chart for Error Detection in Level Mode