The TPS6594-Q1 device includes an over-voltage protection mechanism through a 12-V compliant input monitor at the VSYS_SENSE pin. When an over-voltage is detected at the VSYS_SENSE pin, OVPGDRV pin is pulled low to disable the external high voltage load switch, which connects the VSYS supply to the VCCA pin. After the over-voltage condition is cleared, the voltage at the OVPGDRV pin recovers after the voltage at the VSYS_SENSE pin stays below V_{VSYS_RC_TH} for at least _{VSYS_RC_TH}.

The voltage at the OVPDRV has following relation with the voltage at the VSYS-SENSE pin:

• For VSYS_SENSE < 2.7V: OVPGDRV = 0V
• For 2.7V ≤ VSYS_SENSE ≤ 4.5V: OVPGDRV ≈ 0.9 * 3 * VSYS_SENSE
• For 4.5V < VSYS_SENSE ≤ 6V: OVPGDRV = 12V (in case of a fault in the regulation loop of the internal charge pump, OVPGDRV is limited to 12.5V)
• For VSYS_SENSE > 6V: OVPGDRV = 0V

TI recommends connecting a 10-V zener diode to ground at the VSYS_SENSE pin and one or more series resistors between the VSYS_SENSE pin and the pre-regulator output to limit the current surge and protect the VSYS_SENSE pin from an over-voltage condition due to possible short at the pre-regulator output. The voltage slew rate at the VSYS_SENSE pin must be limited to ≤ V_{VSYS_SR} to prevent possible damage to the device.

After the TPS6594-Q1 device has detected a VCCA over voltage condition, the VCCA domain is unpowered and does not signal the over voltage condition to the VSYS over-voltage protection module. Therefore, a dead-lock mechanism is implemented in the VSYS domain by setting a latch to keep the external high voltage load switch (between VSYS and VCCA) open once the TPS6594-Q1 device has detected a VCCA over voltage condition.

The TPS6594-Q1 first checks for possible fail-short condition of the external FET at initial power up. The diagnostic mechanism pulls the OVPDGRV pin low when VCCA reaches V_{OVP_FET_Short_TH}, and waits until the voltage on the VCCA pin decreases by V_{OVP_FET_Short_Hyst} before it pulls the OVPGDRV pin high again. This mechanism effectively disconnects the VCCA pin from VSYS in case of a FET fail-short condition; with the addition of the diagnostic comparator, however, it also causes a non-monotonic power up behavior with an RC delay at the VCCA pin. The RC-delay is associated with the input capacitance at the VCCA pin and the internal pull-down resistor value R_{VCCA_OVP_PD}.

The comparator module in TPS6594-Q1, which monitors the voltage on the VCCA pins, controls the power state machine of the device. VCCA voltage detection outputs determine the power states of the device as follows:

A separate voltage comparator monitors whether or not the VCCA voltage is within the expected PGOOD range when VCCA is expected to be 5-V or 3.3-V. This voltage comparator checks at device power-up whether the voltage on the VCCA supply pin is above the VCCA_UV threshold. Refer to Section 8.3.4 for additional detail on the operation of the PGOOD monitor function.

LDOVINT, which is the internal supply to the digital core of the device, may attempt to restart the device when the input voltage at VCCA pin falls or stays between VCCA_UVLO and VCCA_UV voltage levels; the voltage at the VCCA pin, however, must be above the VCCA_UV voltage level for the device to power up properly.

Figure 8-1 shows a block diagram of the system input monitoring and over-voltage protection mechanism, and the generation of the VCCA_UVLO and VCCA_OVP power state control signals.

Figure 8-1 VSYS Monitor and OVPGDRV Output Generation