The TPS65981 loads flash memory during the Boot Code sequence. The SPI controller electrical characteristics are defined in SPI Controller Characteristics and timing characteristics are defined in Figure 8-4. The TPS65981 is designed to power the flash from LDO_3V3 to support dead-battery or no-battery conditions, and therefore pull-up resistors used for the flash memory must be tied to LDO_3V3. The flash memory IC must support 12 MHz SPI clock frequency. The size of the flash must be at least 1 Mbyte (equivalent to 8 Mbit) to hold the standard application code outlined in Application Code. The SPI controller of the TPS65981 supports SPI Mode 0. For Mode 0, data delay is defined such that data is output on the same cycle as chip select (SPI_CSZ pin) becomes active. The chip select polarity is active-low. The clock phase is defined such that data (on the SPI_POCI and SPI_PICO pins) is shifted out on the falling edge of the clock (SPI_CLK pin) and data is sampled on the rising edge of the clock. The clock polarity for chip select is defined such that when data is not being transferred the SPI_CLK pin is held (or idling) low. The minimum erasable sector size of the flash must be 4 kB. The W25Q80 flash memory IC is recommended. Refer to TPS65981 I²C Host Interface Specification for instructions for interacting with the attached flash memory over SPI using the host interface of the TPS65981.