The TPS65981 has a Power-on-Reset (POR) circuit that monitors LDO_3V3 and issues an internal reset signal. The digital core, memory banks, and peripherals receive clock and RESET interrupt is issued to the digital core and the boot code starts executing. Figure 9-52 provides the TPS65981 boot code sequence.

The TPS65981 boot code is loaded from OTP on POR, and begins initializing TPS65981 settings. This initialization includes enabling and resetting internal registers, loading trim values, waiting for the trim values to settle, and configuring the device I²C addresses.

The unique I²C address is based on the digital input read on the DEBUG_CTL1/2 pins, which can be tied to GND through a pull-down resistor or to LDO_3V3 through a pull-up resistor.

Once initial device configuration is complete the boot code determines if the TPS65981 is booting under dead battery condition (VIN_3V3 invalid, VBUS valid). If the boot code determines the TPS65981 is booting under dead battery condition, the BUSPOWERZ pin is sampled to determine the appropriate path for routing VBUS power to the system.

Figure 9-52 Flow Diagram for Boot Code Sequence