The TPS65983B application code is stored in an external flash memory. The flash memory used for storing the TPS65983B application code may be shared with other devices in the system. The flash memory organization shown in Figure 9-57 supports the sharing of the flash as well as the TPS65983B using the flash without sharing.

The flash is divided into two separate regions, the Low Region and the High Region. The size of this region is flexible and only depends on the size of the flash memory used. The two regions are used to allow updating the application code in the memory without over-writing the previous code. This ensures that the new updated code is valid before switching to the new code. For example, if a power loss occurred while writing new code, the original code is still in place and used at the next boot.

Figure 9-57 Flash Memory Organization

There are two 4 kB header blocks starting at address 0x000000h. The Low Header 4 kB block is at address 0x000000h and the High Header 4 kB block is at 0x001000h. Each header contains a Region Pointer (RPTR) that holds the address of the physical location in memory where the low region application code resides. Each also contains an Application Code Offset (AOFF) that contains the physical offset inside the region where the TPS65983B application code resides. The TPS65983B firmware physical location in memory is RPTR + AOFF. The first sections of the TPS65983B application code contain device configuration settings. This configuration determines the devices default behavior after power-up and can be customized using the TPS65983B Configuration Tool. These pointers may be valid or invalid. The Flash Read flow handles reading and determining whether a region is valid and contains good application code.